ch01 coa10e stallings

7/25/2019 CH01 COA10e Stallings

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William StallingsComputer Organizationand Architecture10thEdition

2016 Pearson Education, Inc., Hoboken,

NJ. All rights resered.


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Chapter 1Basic Concepts andComputer Evolution

2016 Pearson Education, Inc., Hoboken, NJ. All rights resered.


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Computer Architecture

The operational units and theirinterconnections that realize thearchitectural specifcations

Hardare details transparent tothe programmer! control signals!inter"aces #eteen the computerand peripherals! memor$technolog$ used

%nstruction set! num#er o" #itsused to represent various datat$pes! %&O mechanisms!techni'ues "or addressing memor$

Attri#utes o" a s$stem visi#le tothe programmerHave a direct impact on the logicale(ecution o" a program

Computer

Architecture

Architectural

attributesinclude:

ComputerOrganization

Organization

al attributesinclude:

Computer Organization

2016 Pearson Education, Inc., Hoboken, NJ. All ri hts resered.


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+%B) S$stem

%B) S$stem&*+0 architecture Was introduced in 1,+0

%ncluded a num#er o" models

Could upgrade to a more e(pensive! "aster model ithout havingto a#andon original so"tare

-e models are introduced ith improved technolog$! #ut retainthe same architecture so that the customer.s so"tareinvestment is protected

Architecture has survived to this da$ as the architecture o" %B).s

main"rame product line

*+0 Architecture



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+Structure and /unction

Hierarchical s$stem

Set o" interrelatedsu#s$stems

Hierarchical nature o"comple( s$stems isessential to #oth theirdesign and their description

esigner need onl$ dealith a particular level o" thes$stem at a time

Concerned ith structureand "unction at each level

Structure

The a$ in hich

components relate toeach other

/unction

The operation o"

individual components aspart o" the structure



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+/unction

There are "our #asic "unctions that a computer can per"orm

ata processing

ata ma$ ta2e a ide variet$ o" "orms and the range o"processing re'uirements is #road

ata storage

Short3term

4ong3term

ata movement

%nput3output 5%&O6 3 hen data are received "rom or delivered toa device 5peripheral6 that is directl$ connected to the computer

ata communications 7 hen data are moved over longerdistances! to or "rom a remote device

Control

A control unit manages the computer.s resources andorchestrates the per"ormance o" its "unctional parts in responseto instructions



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Structure

Figure 1.1 A Top-Down View o a Computer

!ainmemor"

#$O

C%&

CO!%&T'(

)"stem*us

A+&(egisters

Control&nit

C%&

#nternal*us

Control &nit(egisters andDecoders

CO,T(O+&,#T

)euencing+ogic

Control!emor"



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+C89 7 controls the

operation o" the computerand per"orms its dataprocessing "unctions

)ain )emor$ 7 stores data

%&O 7 moves data #eteenthe computer and itse(ternal environment

S$stem %nterconnection 7some mechanism thatprovides "or communicationamong C89! main memor$!

and %&O

There are "ourmain structuralcomponents

o" thecomputer



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+C89

Control 9nit

Controls the operation o" the C89

and hence the computer

Arithmetic and 4ogic 9nit 5A496

8er"orms the computer.s dataprocessing "unction

:egisters

8rovide storage internal to theC89

C89 %nterconnection

Some mechanism that provides"or communication among thecontrol unit! A49! and registers

)a;or structural

components



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+)ulticore Computer Structure

Central processing unit 5C896

8ortion o" the computer that "etches and e(ecutes instructions

Consists o" an A49! a control unit! and registers

:e"erred to as a processor in a s$stem ith a single processing unit

Core

An individual processing unit on a processor chip

)a$ #e e'uivalent in "unctionalit$ to a C89 on a single3C89 s$stem

Specialized processing units are also re"erred to as cores

8rocessor A ph$sical piece o" silicon containing one or more cores

%s the computer component that interprets and e(ecutes instructions

:e"erred to as a multicore processor i" it contains multiple cores



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+Cache )emor$

)ultiple la$ers o" memor$ #eteen the processor andmain memor$

%s smaller and "aster than main memor$

9sed to speed up memor$ access #$ placing in thecache data "rom main memor$ that is li2el$ to #e usedin the near "uture

A greater per"ormance improvement ma$ #e o#tained#$ using multiple levels o" cache! ith level 1 5416closest to the core and additional levels 54



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Figure 1. )impli/ed View o !a0or 'lements o a !ulticore Computer

!OT'(*OA(D

%(OC'))O( C#%

CO('

%rocessorchip

!ain memor" chips

#$O chips

Core

+2 cache

#nstructionlogic

+1 #-cache

+ instructioncache

+ datacache

+1 data cache

Arithmeticand logic

unit 3A+&4

+oad$store logic

+2 cache

Core Core Core

Core Core Core Core



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/igure 1=*)other#oard ith To %ntel >uad3Core ?eon

8rocessors 2016 Pearson Education, Inc., Hoboken, NJ. All rights resered.


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/igure 1=@

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