reporte vhd10
DESCRIPTION
practicas realizadas en la clase de vhdl (programacion ) unidad 2 . REALIZADO CON EN Kit basys2TRANSCRIPT
SEP DGEST SNEST
INSTITUTO TECNOLÓGICO DE MATAMOROS
DEPARTAMENTO DE INGENIERÍA ELÉCTRICA Y ELECTRÓNICA
Diseño Digital con VHDL
Equipo:
Alumno(s): Núm. de control:
Mario Arturo Cruz Colunga 11260077
Miguel Angel Fierros Peña 11260081
Hermenegildo Martínez de la Cruz 11260095
Jorge Alejandro Reyes Torres 11260108
H. MATAMOROS, TAM. 1 de Noviembre del 2013
Practica 9
Objetivo:
Realizar la implementación de un reloj que muestre las horas y minutos en formato 24 horas.
Material:
Laptop
Kit spartan3e
Software aldec HDL, xilinx ISE, adept.
Procedimiento:
Se crea nuevo proyecto en aldec HDL
Diagrama bde del reloj
rst clkOut
clk
U1
anodeClock
rst clkOut
clk
U3
clockSecond
startpause
continue
an0an1
rst
clk
an2an3
binaryIn(3:0) sevenSegment(7:0)
U8
binary7decoderbinaryIn(3:0) sevenSegment(7:0)
U6
binary7decoder
sevenOut(7:0)
clk digitOne(3:0)
rst digitTen(3:0)
start digithr00(3:0)
pause digithr11(3:0)
continue
U4
counter7seg
an3 sevenOut(7:0)
an2
an1
an0
sevenOne(7:0)
sevenTen(7:0)
sevenhr0(7:0)
sevenhr1(7:0)
U5
sevenSelect
binaryIn(3:0) sevenSegment(7:0)
U7
binary7decoder
binaryIn(3:0) sevenSegment(7:0)
U9
binary7decoder
clk an0
an1
an2
an3
U2
anodeController
Código clocksecondlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity clockSecond isport (rst : in std_logic;clk : in std_logic;clkOut : out std_logic);end clockSecond;architecture behavioral of clockSecond is-- signal assignmentssignal counter : std_logic_Vector (27 downto 0);signal clkOutSignal : std_logic;beginprocess (clk, rst)beginif (rst = '1') thenclkOutSignal <= '0';counter <= (others => '0');elsif (clk'event and clk = '1') thenif (counter = "1011111010111100001000000")thencounter <= (others => '0');clkOutSignal <= not clkOutSignal;elsecounter <= counter + 1;end if;end if;end process;-- output assignmentsclkOut <= clkOutSignal;end behavioral;
código counter7seg
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity binary7decoder isport (binaryIn : in std_logic_vector (3 downto 0);sevenSegment : out std_logic_vector (7 downto 0));end binary7decoder;architecture behavioral of binary7decoder is-- signal declerations
signal sevenSegmentSignal : std_logic_vector (7 downto 0);beginprocess (binaryIn)begincase binaryIn iswhen "0000" =>sevenSegmentSignal (6 downto 0) <= "1000000";when "0001" =>sevenSegmentSignal (6 downto 0) <= "1111001";when "0010" =>sevenSegmentSignal (6 downto 0) <= "0100100";when "0011" =>sevenSegmentSignal (6 downto 0) <= "0110000";when "0100" =>sevenSegmentSignal (6 downto 0) <= "0011001";when "0101" =>sevenSegmentSignal (6 downto 0) <= "0010010";when "0110" =>sevenSegmentSignal (6 downto 0) <= "0000010";when "0111" =>sevenSegmentSignal (6 downto 0) <= "1111000";when "1000" =>sevenSegmentSignal (6 downto 0) <= "0000000";when others =>sevenSegmentSignal (6 downto 0) <= "0010000";end case;end process;-- dp is always zerosevenSegmentSignal(7) <= '1';-- output assignmentssevenSegment <= sevenSegmentSignal;end behavioral;
código binary7decoder
library IEEE; use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity counter7seg isport (clk : in std_logic;rst : in std_logic;start : in std_logic;pause : in std_logic;continue : in std_logic;digitOne : out std_logic_vector (3 downto 0);digitTen : out std_logic_vector (3 downto 0); digithr00 : out std_logic_vector (3 downto 0);
digithr11 : out std_logic_vector (3 downto 0));end counter7seg;architecture behavioral of counter7seg is-- signal assignmentssignal digitOneSignal : std_logic_vector (3 downto 0);signal digitTenSignal : std_logic_vector (3 downto 0);signal digithr0: std_logic_vector (3 downto 0);signal digithr1 : std_logic_vector (3 downto 0);type states is (resetState, countState, pauseState);signal state : states;beginprocess (clk, rst)beginif (rst = '1') thenstate <= resetState;elsif (clk'event and clk = '1') thencase state iswhen resetState =>digitOneSignal <= (others => '0');digitTenSignal <= (others => '0');if (start = '1') thenstate <= countState;end if;
when countState =>if (pause = '1') thenstate <= pauseState;end if;if (digitOneSignal = "1001") thendigitOneSignal <= (others => '0');digitTenSignal <= digitTenSignal + '1';if (digitTenSignal = "0110") thendigitTenSignal <= (others =>'0');digithr0 <= digithr0 + '1';if (digithr0 ="0101") thendigithr0 <= (others =>'0');digithr1 <= digithr1 + '1';if (digithr1 = "0011")thendigithr1 <= (others =>'0');end if;end if;end if;elsedigitOneSignal <= digitOneSignal + '1';end if;
when pauseState =>
if (continue = '1') thenstate <= countState;end if;end case;end if;end process;-- output signal assignmentsdigitOne <= digitOneSignal;digitTen <= digitTenSignal;digithr00 <= digithr0;digithr11 <= digithr1;end behavioral;
anodecontroller
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity anodeController isport (clk : in std_logic;an0 : out std_logic;an1 : out std_logic;an2 : out std_logic;an3 : out std_logic);end anodeController;architecture behavioral of anodeController is-- signal declerationssignal an0Signal : std_logic;signal an1Signal : std_logic;signal an2Signal : std_logic;signal an3Signal : std_logic;beginprocess (clk)beginif clk'event and clk='1' thenif an3Signal='1' thenan3Signal <= '0';an2Signal <= '1'; an1Signal <= '0';an0Signal <= '0';end if;if an2Signal='1' thenan2Signal <= '0';an1Signal <= '1';an3Signal <= '0';
an0Signal <= '0';end if;if an1Signal='1' thenan1Signal <= '0';an0Signal <= '1';an2Signal <= '0';an3Signal <= '0';end if;if an0Signal='1' thenan0Signal <= '0';an3Signal <= '1';an3Signal <= '0';an3Signal <= '0';end if;end if;end process;an0 <= not an0Signal;an1 <= not an1Signal;an2 <= not an2Signal;an3 <= not an3Signal;end behavioral;
anodeclock
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity anodeClock isport (rst : in std_logic;clk : in std_logic;clkOut : out std_logic);end anodeClock;architecture behavioral of anodeClock is-- signal assignmentssignal counter : std_logic_Vector (19 downto 0);signal clkOutSignal : std_logic;beginprocess (clk, rst)beginif (rst = '1') thenclkOutSignal <= '0';counter <= (others => '0');elsif (clk'event and clk = '1') thenif (counter = x"c350")thencounter <= (others => '0');
clkOutSignal <= not clkOutSignal;elsecounter <= counter + 1;end if;end if;end process;clkOut <= clkOutSignal;end behavioral;
código sevenselect
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity sevenSelect isport (an3 : in std_logic;an2 : in std_logic;an1 : in std_logic;an0 : in std_logic;sevenOne : in std_logic_vector (7 downto 0);sevenTen : in std_logic_vector (7 downto 0); sevenhr0 : in std_logic_vector (7 downto 0);sevenhr1 : in std_logic_vector (7 downto 0);sevenOut : out std_logic_vector (7 downto 0));end sevenSelect;architecture behavioral of sevenSelect issignal sevenOutSignal : std_logic_vector (7 downto 0);beginprocess (an0,an1,an2, an3,sevenhr0,sevenhr1, sevenOne, sevenTen)beginif (an3 = '0') thensevenOutSignal <= sevenone;elsif (an2='0') then sevenOutSignal <= seventen;elsif (an1='0') thensevenoutsignal <= sevenhr0;elsesevenoutsignal <= sevenhr1;end if;end process;sevenOut <= sevenOutSignal;end behavioral;
Observaciones y conclusiones: El programa realiza la función de un reloj, contando las horas y minutos en formato de 24 horas, se realizó mediante la modificación de la práctica del cronometro.