electronica digital aplicada

ElectrónicaDigital

Aplicada

Pedro J. Sotorrío RuizDiciembre 2013

Electrónica Digital Aplicada

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Índice general:

Capítulo 1.- Presentación

Capítulo 2.- Conceptos y Elementos básicos

Capítulo 3.- Dispositivos combinacionales

Capítulo 4.- Dispositivos secuenciales

Capítulo 5.- Dispositivos computacionales

Capítulo 6.- Dispositivos de Memoria

Capítulo 7.- Dispositivos Periféricos

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1.1.- Objetivos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2

1.2.- Sobre la Electrónica Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2

1.3.- Sistemas Digitales . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3

1.4.- Tecnologías . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4

1.5.- Sobre las referencias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6

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1.1.- Objetivos

De todos es sabido que la adquisición de conocimiento es un procesoacumulativo: lo que eres capaz de aprender ahora está soportado por lo que ya sabes.Este hecho es muy importante y marca todo el proceso de aprendizaje en cualquiermateria. La Electrónica Digital es una técnica que no escapa a este proceso, por esoes muy importante disponer de unas bases sólidas.

El objetivo de este documento es que el lector pueda realizar una aproximaciónde la parte teórica de la Electrónica Digital y la realidad industrial de la misma. Paraello, tras una breve introducción a la técnica en cada capítulo, pasamos a utilizardispositivos reales disponibles en el mercado. Es por eso que este documento es, enparte, una recopilación de dispositivos digitales típicos para la realización de circuitosdigitales avanzados.

1.2.- Sobre la Electrónica Digital

La Electrónica Digital es una técnica y como tal consta de una serie de reglas queactualmente son bien conocidas y eso ayuda mucho a su comprensión.Afortunadamente disponemos de muy buena documentación bibliográfica y no tienesentido ampliar en este sentido.

Por otro lado, la Electrónica Digital se fundamenta en tres apartados: Electricidad,Electrónica de conmutación y Álgebra binaria. Por eso es necesario disponer de:

• Conocimientos amplios de las bases de Electricidad ya que serán utilizadospermanentemente. Más concretamente es necesario tener conocimientosde la teoría de circuitos.

• Conocimientos en el área de Electrónica de Conmutación, que es un casoparticular de Electrónica Analógica en cuanto que los transistores trabajanúnicamente en las zonas de corte y saturación.

• Conocimientos del álgebra binaria ya que es la base de casi todas lasaplicaciones reales.

En ningún caso, podemos olvidar que:

• La Electrónica es una rama de una ciencia más extensa denominadaElectricidad y sus bases son las mismas. Por eso en muchos casos

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tendremos que utilizar conceptos de electricidad ya que los esquemas soneléctricos aunque los denominamos electrónicos para diferenciarlos.

• La Electrónica Digital (ED) es un caso particular de la Electrónica Analógica(EA) de la que procede cuando los elementos activos (transistores) trabajanúnicamente en la zona de corte y de saturación, no utilizando la zona activacomo se hace en EA. Sin embargo, para pasar del estado de corte al desaturación y viceversa, los transistores necesitan pasar por la zona activa defuncionamiento. Esto nos traerá ciertos problemas que analizaremosdetalladamente.

• Los comentarios de los apartados anteriores son importantes en los casosreales ya que afectan al comportamiento de los elementos. Sin embargo,nosotros suponemos, inicialmente, que no afecta para nada el tránsito porla zona activa y sólo trabajamos en las de corte y saturación. Esta es unasimplificación muy importante para avanzar en la comprensión de las basesy de los elementos básicos de ED. Más adelante veremos que la circuiteríareal no puede eludir la existencia de la zona lineal y, como consecuencia, elcomportamiento de los dispositivos no es tan ideal como asumimos.

1.3.- Sistemas Digitales

Los Sistemas Electrónicos Digitales son siempre complejos. Se basan enconceptos simples agrupados de determinadas formas para obtener los resultados quese pretenden. Como en toda técnica, en ED se definen los elementos básicos y sobreestas definiciones se construyen los elementos complejos. Un simil mecánico puedeser el de un dispositivo complejo como el motor de un vehículo que se basa enelementos simples como ejes, ruedas, palancas, etc.

En el caso que nos atañe, Electrónica Digital, la forma de construir es idéntica;unos elementos de base y el apilamiento ordenado de estos elementos da lugar asistemas más complejos. Los elementos de base son simples y fáciles de entendermientras que las reglas de construcción son algo más complejas, pero en ningún casodejan de ser técnicas.

Esta filosofía de construcción es la que utilizamos para obtener los SistemasElectrónicos Digitales Complejos. Utilizando elementos bien conocido y disponibles enel mercado, los agrupamos para obtener nuestro objetivo. Esta técnica es similar a laque utilizan los bricoleros: utilizando los medios disponibles hacemos nuevas cosas.

La técnica DIY (Do It Yourself) o HTM (Hazlo Tú Mismo) la utilizamos aquí en elsentido de construir las distintas partes de un sistema electrónico digital condispositivos ya existentes y conocidos. Todos los elementos necesarios para haceresto ya deben de ser conocidos cuando se aborda el estudio de los SBM (SistemasBasados en Microprocesadores, una asignatura del 2º cuatrimestre). En estos sistemasno hay circuitos nuevos sino configuraciones nuevas, es decir, formas diferentes deconexión de los elementos disponibles para formar un nuevo elemento y algunos

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conceptos nuevos.

Por ello, es necesario conocer los circuito básicos. Este conocimiento implica larápida identificación del gráfico que lo representa y la asociación con sufuncionamiento por medio de los correspondientes cronogramas funcionales. Como severá más adelante, conforme los elementos adquieren complejidad funcional, suesquema electrónico deja de ser importante y adquiere un papel fundamental sucronograma funcional. Esto es así hasta tal punto que los fabricantes de sistemasmedianamente complejos no suministran más que un pequeño diagrama de bloquesjunto a una breve descripción funcional y su cronograma.

Por medio de la técnica HTM construimos elementos cada vez más complejossiempre en base a los elementos fundamentales que se describen en los capítulos quesiguen.

1.4.- Tecnologías

Para la realización de los diferentes circuitos digitales que se verán en loscapítulos siguientes se utilizan diferentes tecnologías. La figura 1.1 resume unacolección de tecnología utilizadas por Texas Instruments para realizar sus circuitosdigitales. En esta figura podemos ver que las tensiones de funcionamiento son de 1.8V,3.3V, 5V y 10V. Dentro de cada valor de tensión encontramos diferentes dispositivos(columnas) y diferentes tecnologías (filas) cuya nomenclatura son los acrónimos (conexcepciones) que la definen como sigue:1.8V AUC - Advanced Ultra-Low-Voltage CMOS Logic

AUP - Advanced Ultra-Low-Power CMOS Logic

3.3V ALVC - Advanced Low-Voltage CMOS TechnologyAVC - Advanced Very-Low-Voltage CMOS LogicLV-A - Low-Voltage CMOS TechnologyLV-AT - Low-Voltage CMOS TechnologyLVC - Low-Voltage CMOS TechnologyALB - Advanced Low-Voltage BiCMOSALVT - Advanced Low-Voltage CMOS TechnologyLVT - Low-Voltage BiCMOS TechnologyCB3Q - Low-Voltage, High-Bandwidth Bus Switch TechnologyCB3T - Low-Voltage, Translator Bus Switch

TechnologyCBTLV - Low-Voltage Crossbar TechnologyGTL - Gunning Transceiver LogicGTLP - Gunning Transceiver Logic PlusTS - TI SwitchTVC - Translation Voltage ClampVME - VME Bus Products

5V AC - Advanced CMOS LogicACT - Advanced CMOS LogicAHC - Advanced High-Speed CMOSAHCT - Advanced High-Speed CMOSFCT - Fast CMOS TechnologyHC - High-Speed CMOS LogicHCT - High-Speed CMOS LogicABT - Advanced BiCMOS TechnologyABTE - Advanced BiCMOS Technology /

Enhanced Transceiver LogicBCT - BiCMOS TechnologyALS - Advanced Low-Power Schottky LogicAS - Advanced Schottky LogicF - Fast LogicLS - Low-Power Schottky LogicS - Schottky LogicTTL - Transistor-Transistor LogicCBT - Crossbar TechnologyCBT-C - CBT with Undershoot ProtectionFB - Backplane Transceiver LogicTS - TI Switch

10V CD4000 - CMOS

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Figura 1.1. Familias de circuitos digitales.

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Estas nomenclatura son de este fabricante. Otros fabricantes tienen otras quepueden no coincidir con este caso. Sin embargo las que coinciden tienen las mismascaracterísticas básicas y suelen ser compatibles.

Las distintas familias de circuitos presentan distintas características no solo en latensión de alimentación sino en otros parámetros como los tiempos de conmutaciónretardos, consumos, etc. En cada ocasión debemos seleccionar la tecnología quemejor responda a las características específica de nuestro diseño.

1.5.- Sobre las referencias

Al final de cada capítulo se ha incluido un conjunto de referencias que no son más(ni menos) que las hojas de características suministradas por los fabricantes de losdispositivos tomados como ejemplos. Hay que hacer notar que esta referencias puedenestar recortadas en cuanto a que se han eliminado las páginas referidas acaracterísticas mecánicas, embalajes, codificación y temas no relacionadosexclusivamente con Electrónica Digital. De esta forma se han ahorrado muchaspáginas que no resultan útiles en este momento.

Además de las referencias en cada capítulo, hay tres referencias comunes a librosya publicados que forman la base y son los siguientes:

1. Fundamentos de Sistemas Digitales, Thomas L. Floyd, Edición 7ª, PrenticeHall. ISBN: 84-205-2994-X.

2. Sistemas Basados en Microprocesadores, Pedro J. Sotorrío, Eduardo Ruizy Juan M. Romero, UMA 2004, ISBN: 84-9749-009-5. Reimpresión 2013 enCopicentro.

3. Diseño Práctico de SBM, Pedro J. Sotorrío, Eduardo Ruiz, 2001, ISBN: 84-699-4314-6. Reimpresión 2013 Copicentro.

El primero de ellos es el más clásico utilizado en las Universidades Españolasmientras que los otros dos está específicamente desarrollados para la docencia deSBM en la UMA. En la referencia 2 se describe el funcionamiento de un :P desde suinterior, permitiendo al alumno construir su propio sistema.

NOTA: Todas las referencias citadas son propiedad de los correspondientesautores.

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Capítulo 2.- Conceptos y Elementos básicos2.1.- Conceptos básicos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2

2.1.1.- Nomenclatura . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2

2.1.2.- Niveles digitales . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3

2.1.3.- Representación gráfica de los niveles digitales . . . . . . . . . . . . 2.4

2.1.4.- Representación gráfica de los buses . . . . . . . . . . . . . . . . . . . . 2.5

2.1.5.- Tipos de salida . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6

2.2.- Componentes básicos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7

2.3.- Dispositivos especiales . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10

2.4.- Referencias del capítulo 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.13

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Tema 2.- Conceptos y Elementos básicosComo se ha descrito en el apartado anterior, la técnica DIY utiliza elementos

simples para construir otros más complejos. Es por ello que en este apartado vamosa recordar los elementos básicos que utilizaremos así como algunos conceptosnecesarios y su realización electrónica.

2.1.- Conceptos básicos

Empezamos por describir algunos conceptos básicos que deben de ser conocidospara poder avanzar en el resto de temas:

2.1.1.- Nomenclatura

Para poder entendernos con facilidad necesitamos definir el protocolo que vamosa utilizar. Al igual que en otras especialidades, en ED existe un argot propio que esnecesario conocer para no confundir los conceptos. En lo que sigue hacemos unaintroducción a la nomenclatura que utilizamos en este documento y que secorresponde con la habitual en ED. Cuando sea posible, describiremos lanomenclatura en Español y en Inglés para que se vea la correlación entre lasexpresiones. No se trata de hacer un diccionario sino de describir la forma de hacer lascosas.

Niveles digitales: Es muy habitual representarlos por los símbolos numéricos “1"y “0" pero técnicamente es más correcto utilizar las letras “H” (High) para el nivelalto o “1" y “L” (Low) para el nivel bajo o “0". De hecho el la información técnicaprofesional se utiliza esta última nomenclatura. Como se verá mas adelante,también utilizamos un pseudo nivel que denominamos triestado (three state)y quese representa con la letra “Z”.

Señales: Una señal se identifica por medio de una o varias letras que constituyesu nombre. Conviene que el nombre de las señales tenga relación con su función.Lo más usual es utilizar una palabra o un acrónimo que nos recuerde para lo quese utiliza la señal. Por ejemplo, en SED se utiliza muchas señales que sedenominan /RD (ReaD, lectura), /WR (WRite , escritura), /CS (Chip Select,selección de dispositivo),... Aunque podemos asignar cualquier otro nombre, losutilizados habitualmente presentan la ventaja de ser fácilmente comprendidos.

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Como podemos ver, en los nombre de las señales citadas antes hay una barra “/”delante del nombre. Esto es para indicar que el estado activo de esta señal es elnivel “L”. Por lo tanto, el nivel “H” es el estado de reposo. Esta nomenclatura seutiliza en señales que actúan o controlan algo. En señales que forman parte deun conjunto numérico (un dato binario), esta barra no se pone ya que no esrelevante.

Buses: Para nosotros un BUS es un conjunto de señales homogéneas o no. Enlos sistemas digitales complejos es muy frecuente agrupar las señales en buses.Cada una de las señales de un bus tiene su propio nombre que es necesarioidentificar con vista a que cualquier lector del documento que sea pueda entenderlas explicaciones, los cronogramas o los esquemas, según correspondan.

Los nombres de las señales dentro de un bus se establecen con el mismo criterioque se ha descrito en el apartado anterior. Sin embargo, cuando el conjunto detodas las señales de un bus forman una única información (típicamentenumérica), que es el caso de los buses homogéneos, los nombres de las señalessuelen tener una raíz común y un número asociado que las distingue unas deotras. Así por ejemplo, un bus de direcciones de 16 bits se suele denominarABUS y sus señales se denominan A15, A14, A13, ..., A3, A2, A1 y A0. Observarque la numeración va de n-1 hasta 0 ya que la primera combinación válida es el0 y no el 1. De hecho, el sistema de numeración decimal no va de 1 a 10 sino de0 a 9. El número 10 es una combinación de dos símbolos numéricos y no formaparte de la base.

2.1.2.- Niveles digitales

En electrónica digital trabajamos con dos valores eléctricos que identificamos conlos símbolos 1 y 0 y que habitualmente asociamos con un valor alto y un valorbajo de la tensión respectivamente en el punto que se trata. Esto no esestrictamente cierto y por eso el título de este apartado habla de Niveles y no devalores. Los niveles son un conjunto de valores para los cuales se cumple lacondiciones funcionales.

Nivel bajo (L) o “0" digital : Concretamente, hablando de un sistema quefunciona a 5V (entre 0 y 5V), el símbolo binario “0" se representaeléctricamente por medio de un conjunto de valores de tensión entre 0.0Vy 0.4V para las tensiones de entrada y entre 0.0V y 0.8V para las tensionesde salida. Así pues, cuando la salida de un circuito digital está en el estadobajo, eléctricamente esta salida tiene una tensión comprendida entre 0.0Vy 0.4V y se denomina VoL. Cuando en una entrada tenemos un nivel bajo,la tensión en ella ha de estar comprendida entre 0.0V y 0.8V y se denominaViL. Así, por ser ViLmax > VoLmax, se asegura un margen de error de 0.4V

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(mínimo).

Nivel alto (H) o “1" digital : De forma similar a lo dicho en el párrafoanterior, los valores de tensiones para el nivel alto a la tensión dealimentación de 5V) son de 2.0V a 5.0V para el nivel alto de entrada (ViH) y3.0V a 5.0V para el nivel alto de salida (VoH). En este caso el margen deseguridad es de 1V (VoH - ViH).

Cuando los niveles de tensión digitales tienen otros valores (3.3V, 12V, etc),las definiciones de los niveles alto y bajo son diferentes.

Tercer “nivel” digital: Se denomina así al estado de desconexión de lasalida de un circuito. Hay multitud de ocasiones en que es necesariodesconectar la salida de un dispositivo y esto se hace por medio de unaseñal que controla este estado. Como es fácil de comprobar no se tratarealmente de un “estado” digital en sí mismo ya que por el hecho de estarun dispositivo desconectado no aporta información binaria (“0" o “1"). Sinembargo es muy cómodo utilizar la expresión de “tercer nivel” y como tal loutilizaremos teniendo claro su concepto. Este tercer nivel recibe el nombrede desconexión lógica (no física) o triestado (Three state) y se representacon la letra “Z”.

2.1.3.- Representación gráfica de los niveles digit ales

En Electrónica Digital, como en otras ciencias, se trabaja mucho con gráficosporque las descripciones funcional verbal es realmente complicada de hacer.

La representación gráfica de las distintas combinaciones funcionales posibles delas señales de un dispositivo puede ser muy compleja y ello depende de lafuncionalidad del propio dispositivo. Sin embargo estas representaciones gráficasdenominadas cronogramas, describen la evolución de las señales a lo largo deltiempo de una forma simple.

Un cronograma no es más que la representación en el eje del tiempo (eje x) dela evolución de los valores digitales de las señales que tiene un dispositivo digital.En sí mismo, los cronogramas definen la funcionalidad de los dispositivos desdeel punto de vista de la circuitería (hardware).

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Figura 2.1. Representación gráfica de los niveles en una señal digital.

Figura 2.2. Cronograma de buses homogéneos. a) bus sin desconexión, b)bus con desconexión.

En la figura 2.1 se han representado los niveles de una señal que evolucionaentre los tres niveles citados antes: durante los intervalos A y D, la señal seencuentra a nivel alto “H”; durante el intervalo B, la señal se encuentra a nivel bajo“L” y durante los intervalos C y E, la señal se encuentra en desconexión “Z”.

2.1.4.- Representación gráfica de los buses

Dado que un bus es un conjunto de señales, cuando el bus es homogéneo (todaslas señales están relacionadas formando una sola información), el conjunto del bus serepresenta de una forma simplificada como se ha representado en la figura 2.2. En lafigura 2.2a) se ha representado un bus típico de direcciones compuesto de 16 señales(A15 - A0) sin triestado. En esta figura hay marcadas 5 zonas: las zonas 2 y 4representan los intervalos de cambios en el bus. No significa que todas las señales delbus cambien de nivel, con que haya una sola señal que lo haga ya ha cambiado elconjunto (el valor numérico representado por las señales del bus) y por lo tanto estaes su representación. Observar que entre la zona 1 y la 3 sólo cambia un bit (A0 pasade L a H), mientras que entre la zona 3 y la 5 cambian bastantes bits. Es por esto porlo que entre las dos líneas de la representación se coloca el valor del conjunto deseñales (valor del bus) durante ese periodo de tiempo. Observar que los valores seindican en hexadecimal, nunca en decimal ni en binario. Durante los intervalos detránsito (2 y 4) no es conocido el valor del bus. Estos intervalos de tránsito son muyEl

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Figura 2.3. Esquemaeléctrico de la etapa desalida Totem-Pole.

cortos (alguna decena de ns) pero eso no les resta importancia y por eso hay querepresentarlos.

La figura 2.2 b) representa un bus con triestado (desconexión). Es el caso típicode un bus de datos de un SBM. Los intervalos de tiempo 2, 4, 6 y 8 representan losintervalos en los que el contenido del bus está cambiando. Su valor es desconocido.En los intervalos 1 y 9 el bus se encuentra desconectado y se representa por mediode una línea horizontal entre el nivel H y el nivel L (este es el nivel “Z” citado antes). Enlos intervalos 3, 5 y 7 el valor del bus es estable y en la figura se ha colocado su valornumérico. Observar que los valores se indican en hexadecimal, nunca en decimal nien binario.

2.1.5.- Tipos de salida

Las etapas de salida de un circuito digital presentan tres tipos de salida cuyascaracterísticas funcionales son muy diferentes y por ello se utilizan para aplicacionesespecíficas.

Salida “Totem-Pole”: El circuito de salida con dos transistores representado enla figura 2.3 recibe el nombre de “Totem.Pole”. Este tipo de salida tiene comocaracterística que la señal procedente de él presenta siempre baja impedancia yase encuentre a nivel H o a nivel L. Esto es importante para asegurar los nivelesdigitales correctos en la mayoría de las aplicaciones. Es por eso que casi todaslas etapas de salida disponen de este tipo de salida.

En la figura 2.3 se puede ver el esquema eléctrico de esta etapa. La señalprocedente de la etapa anterior (que es la que realiza la función digital que lecorresponda) llega a esta etapa de salida haciendo que sólo uno de lostransistores de salida T3 y T4 se mantenga en conducción en cada nivel.

Salida en colector abierto: Es tipo de salida es el mostrado en la figura 2.4. Enella podemos ver que la señal de salida se conecta directamente al colector y enél no hay otras conexiones. Este tipo de salida se utiliza en algunas ocasiones

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Figura 2.4. Esquema eléctricode la etapa de salida encolector abierto.

Figura 2.5. Esquema eléctrico de laetapa de salida Totem-Pole condesconexión (triestado).

pero no es la más frecuente en ED.

Salida triestado: Es el tipo de salida que permite disponer del estado dedesconexión citado anteriormente. La figura 2.5 muestra el esquema de este tipode salida que dispone de una señal de control adicional que permite desconectarlógicamente (no físicamente) el dispositivo sin realizar una desconexión física.Este tipo de salida se utiliza mucho en SBM en donde las conexiones por mediode buses es muy frecuente.

2.2.- Componentes básicos

En lo que sigue describimos los elementos básicos ya conocidos por todos y surealización por medio de circuitos electrónicos. En todos los casos hacemos uso dereferencias a las hojas de características suministradas por algunos fabricantes parapoder contrastar la información.

Inversor: En electrónica digital, un inversor es un dispositivo cuyo valor eléctricode salida es el inverso (desde el punto de vista binario), es decir que si a suentrada hay un “1", a su salida hay un “0" y si en su entrada es “0", en su salida

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Figura 2.6. Cronograma del inversor.

E S

0 1

1 0

Figura 2.7. Esquema de un inversor digital y

su símbolo

A B Salida

0 0 0

0 1 0

1 0 0

1 1 1

Figura 2.8. Cronograma de la función AND.

hay un “1". Como sabemos, esto se representa por medio de una tabla de verdadcomo sigue:

donde E es la señal de entrada y S es la señal de salida.

También podemos representar su funcionamiento por medio de uncronograma como el de la figura 2.6. La figura 2.7 muestra un esquemaelectrónico que realiza la función inversión. En esta figura también podemos verel símbolo que se utiliza para representarlo.

Ver la referencia 74LS04.

AND: El funcionamiento de una función AND de dos entradas (A y B) se describepor medio de la tabla de verdad y el cronograma siguiente:

donde la salida sólo toma el valor binario “1" cuando en ambas entradas tenemosun valor binario “1". La figura 2.9 muestra un esquema electrónico que realizaesta función digital y su representación.

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Figura 2.9. Esquema eléctrico de una función AND de dos entradas y susímbolo.

A B S

0 0 1

0 1 1

1 0 1

1 1 0Figura 2.10. Símbolo y cronograma de una funciónNAND.

Figura 2.11. Tabla de verdad,símbolo y cronograma de la función OR.

A B S

0 0 0

0 1 1

1 0 1

1 1 1


NAND: Esta es una función cuya tabla de verdad (para dos entradas) es:

Como puede verse, es la función inversa de la función AND. Su circuito sepuede realizar conectando en serie el circuito de la función AND y el del inversorvistos antes. Su representación es la que se muestra en la figura 2.10, dondetambién se ha representado un cronograma de funcionamiento.


OR: La función OR de dos entradas se define por medio de la tabla de verdadsiguiente:

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Figura 2.12. Esquema eléctrico deuna función OR de dos entradas

Figura 2.13. Tabla de verdad,símbolo y cronograma de lafunción NOR.

A B S

0 0 1

0 1 0

1 0 0

1 1 0

A B S

0 0 0

0 1 1

1 0 1

1 1 0

Figura 2.14. Tabla de vardad ycronograma de la función XOR

La figura 2.11 muestra el símbolo que la representa y un cronograma defuncionamiento. La figura 2.12 muestra un esquema eléctrico que realiza estafunción lógica.


NOR: Esta función es la complementaria (inversa) de la función OR. Su tabla deverdad y cronograma funcional es:

La figura 2.13 contiene el símbolo y un cronograma funcional de una puertaNOR. Ver la referencia 74LS02.

XOR: Esta función lógica se define por medio de su tabla de verdad y elcronograma siguiente:

El esquema lógico de esta función es el representado en la figura 2.15 juntoa su símbolo.

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Figura 2.15. Esquema lógico y símbolo de la función XOR.

Ver la referencia 74HCT86.

2.3.- Dispositivos especiales

Por dispositivos especiales entendemos aquellos que no siendo pertenecientesa la realización de los conceptos básicos de funciones booleanas, son necesarios paraaplicaciones en general y en SBM en particular.

Amplificador binario unidireccional: Se trata de un dispositivo que amplifica laseñal binaria. Como no se puede amplificar en tensión ya que los valores de losniveles digitales se establecen por tensión, se amplifica en corriente. Es decir sondispositivos que son capaces de suministrar una “alta corriente” frente a losdispositivos normales. El término alta corriente se ha situado entre comillas yaque en electrónica digital una corriente alta puede ser de tan solo unas decenasde miliamperios. De hecho los dispositivos que vemos a continuación suministrana su salida unos 24 mA.

• Dispositivo 74LS244: La figura 2.16 es el esquema digital de estedispositivo.

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V1.0 2.12

Figura 2.16. Esquema digital del dispositivo 74LS244.

En esta figura podemos ver que el dispositivo se compone de dos partesindependientes. Cada una de ellas consta de cuatro amplificadores digitales consalida triestado. Si vemos en la referencia 74LS244, veremos que el fabricante lodenomina como “Octal Buffers And Line Drivers With 3-state Outputs”, lo quesignifica que se trata de un conjunto de ocho amplificadores digitales con salidatriestado. Atención a la palabra “buffer” que tiene muchos significados dentro dela ED. De hecho estos dispositivos se utilizan mucho para hacer las interfases conlos buses de un SBM.

• Dispositivo 74LS240: Es similar al dispositivo 74LS244 pero tiene la salidainvertida respecto a la entrada. Ver la referencia 74LS244.El

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V1.0 2.13

Figura 2.17. Esquema digital del dispositivo 74LS245.

Amplificador binario bidireccional: Se trata de un dispositivo amplificados comoel caso del 74LS244 pero que además permite que las señales fluyan en los dossentidos posibles un una conexión (no simultáneamente). El dispositivo masclásico es el 74LS245, cuyo esquema digital lo podemos ver en la figura 2.17.

En esta figura podemos ver que además de una señal para controlar ladesconexión del dispositivo (/OE) también hay una señal para controlar el sentidode la información (DIR), de tal que si DIR = H la información fluye de losterminales An hacia los terminales Bn y si DIR = L la información fluye desde losterminales Bn hacia los terminales An. A esto se denomina “bidireccional”.Observando la figura y comparándola con la del 74LS244 (figura 2.16), podemosconcluir que este dispositivo se basa en disponer de dos 74LS244 conectados enoposición y con un control de activación.


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2.4.- Referencias del capítulo 2El

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SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Package Options Include PlasticSmall-Outline (D, NS, PS), ShrinkSmall-Outline (DB), and Ceramic Flat (W)Packages, Ceramic Chip Carriers (FK), andStandard Plastic (N) and Ceramic (J) DIPs

Also Available as Dual 2-InputPositive-NAND Gate in Small-Outline (PS)Package

SN5400 . . . J PACKAGESN54LS00, SN54S00 . . . J OR W PACKAGE

SN7400, SN74S00 . . . D, N, OR NS PACKAGESN74LS00 . . . D, DB, N, OR NS PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A1B1Y2A2B2Y

GND

VCC4B4A4Y3B3A3Y

SN5400 . . . W PACKAGE(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A1B1Y

VCC2Y2A2B

4Y4B4AGND3B3A3Y

SN74LS00, SN74S00 . . . PS PACKAGE(TOP VIEW)

1

2

3

4

8

7

6

5

VCC2B2A2Y

1A1B1Y

GND

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

4ANC4YNC3B

1YNC2ANC2B

1B 1A NC

3Y 3AV 4B

2YG

ND

NC

SN54LS00, SN54S00 . . . FK PACKAGE(TOP VIEW)

CC

NC − No internal connection

description/ordering information

These devices contain four independent 2-input NAND gates. The devices perform the Boolean functionY = A • B or Y = A + B in positive logic.

Copyright 2003, Texas Instruments Incorporated ! "#$ ! %#&'" ($)(#"! " !%$""! %$ *$ $! $+! !#$!!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($$!. '' %$$!)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

%(#"! "%' / 0121 '' %$$! $ $!$(#'$!! *$,!$ $() '' *$ %(#"! %(#"%"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)

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2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

ORDERING INFORMATION

TA PACKAGE † ORDERABLEPART NUMBER

TOP-SIDEMARKING

SN7400N SN7400N

PDIP − N Tube SN74LS00N SN74LS00NPDIP − N Tube

SN74S00N SN74S00N

Tube SN7400D7400

Tape and reel SN7400DR7400

SOIC − DTube SN74LS00D

LS00SOIC − DTape and reel SN74LS00DR

LS00

0°C to 70°C Tube SN74S00DS00

0 C to 70 C

Tape and reel SN74S00DRS00

SN7400NSR SN7400

SOP − NS Tape and reel SN74LS00NSR 74LS00SOP − NS Tape and reel

SN74S00NSR 74S00

SOP − PS Tape and reelSN74LS00PSR LS00

SOP − PS Tape and reelSN74S00PSR S00

SSOP − DB Tape and reel SN74LS00DBR LS00

SNJ5400J SNJ5400J

CDIP − J Tube SNJ54LS00J SNJ54LS00JCDIP − J Tube

SNJ54S00J SNJ54S00J

−55°C to 125°CSNJ5400W SNJ5400W

−55°C to 125°CCFP − W Tube SNJ54LS00W SNJ54LS00WCFP − W Tube

SNJ54S00W SNJ54S00W

LCCC − FK TubeSNJ54LS00FK SNJ54LS00FK

LCCC − FK TubeSNJ54S00FK SNJ54S00FK

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelinesare available at www.ti.com/sc/package.

FUNCTION TABLE(each gate)

INPUTS OUTPUTA B

OUTPUTY

H H L

L X H

X L H

logic diagram, each gate (positive logic)

A

BY

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schematic

’00

GND

Y

130 Ω

VCC

4 kΩ

A

1.6 kΩ

1 kΩ

B

VCC

Resistor values shown are nominal.

Y

GND

3 kΩ

4 kΩ

120 Ω8 kΩ20 kΩ

1.5 kΩ

12 kΩ

A

B

2.8 kΩ 900 Ω

B

A

500 Ω 250 Ω

3.5 kΩ

’LS00 ’S00

VCC

Y

GND

50 Ω

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absolute maximum ratings over operating free-air temperature (unless otherwise noted) †

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage: ’00, ’S00 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

’LS00 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS package 95°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.2. The package termal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN5400 SN7400UNIT

MIN NOM MAX MIN NOM MAXUNIT

VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.8 0.8 V

IOH High-level output current −0.4 −0.4 mA

IOL Low-level output current 16 16 mA

TA Operating free-air temperature −55 125 0 70 °C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)

PARAMETER TEST CONDITIONS‡SN5400 SN7400

UNITPARAMETER TEST CONDITIONS‡MIN TYP§ MAX MIN TYP§ MAX

UNIT

VIK VCC = MIN, II = −12 mA −1.5 −1.5 V

VOH VCC = MIN, VIL = 0.8 V, IOH = −0.4 mA 2.4 3.4 2.4 3.4 V

VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V

II VCC = MAX, VI = 5.5 V 1 1 mA

IIH VCC = MAX, VI = 2.4 V 40 40 µA

IIL VCC = MAX, VI = 0.4 V −1.6 −1.6 mA

IOS¶ VCC = MAX −20 −55 −18 −55 mA

ICCH VCC = MAX, VI = 0 V 4 8 4 8 mA

ICCL VCC = MAX, VI = 4.5 V 12 22 12 22 mA

‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.§ All typical values are at VCC = 5 V, TA = 25°C.¶ Not more than one output should be shorted at a time.

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switching characteristics, V CC = 5 V, TA = 25°C (see Figure 1)

PARAMETERFROM

(INPUT)TO

(OUTPUT)TEST CONDITIONS

SN5400 SN7400 UNITPARAMETER

(INPUT) (OUTPUT)TEST CONDITIONS

MIN TYP MAX

UNIT(INPUT) (OUTPUT)

MIN TYP MAX

tPLHA or B Y RL = 400 Ω, CL = 15 pF

11 22ns

tPHLA or B Y RL = 400 Ω, CL = 15 pF

7 15ns


SN54LS00 SN74LS00UNIT










PARAMETER TEST CONDITIONS†SN54LS00 SN74LS00

UNITPARAMETER TEST CONDITIONS†MIN TYP‡ MAX MIN TYP‡ MAX

UNIT

VIK VCC = MIN, II = −18 mA −1.5 −1.5 V

VOH VCC = MIN, VIL = MAX, IOH = −0.4 mA 2.5 3.4 2.7 3.4 V

VOL VCC = MIN, VIH = 2 VIOL = 4 mA 0.25 0.4 0.25 0.4

VVOL VCC = MIN, VIH = 2 VIOL = 8mA 0.35 0.5

V

II VCC = MAX, VI = 7 V 0.1 0.1 mA

IIH VCC = MAX, VI = 2.7V 20 20 µA

IIL VCC = MAX, VI = 0.4 V −0.4 −0.4 mA

IOS§ VCC = MAX −20 −100 −20 −100 mA

ICCH VCC = MAX, VI = 0 V 0.8 1.6 0.8 1.6 mA

ICCL VCC = MAX, VI = 4.5 V 2.4 4.4 2.4 4.4 mA

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time.


PARAMETERFROM

(INPUT)TO


SN54LS00 SN74LS00 UNITPARAMETER


MIN TYP MAX


MIN TYP MAX

tPLHA or B Y RL = 2 kΩ, CL = 15 pF

9 15ns

tPHLA or B Y RL = 2 kΩ, CL = 15 pF

10 15ns

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SN54S00 SN74S00UNIT





IOH High-level output current −1 −1 mA





PARAMETER TEST CONDITIONS†SN54S00 SN74S00


UNIT

VIK VCC = MIN, II = −18 mA −1.2 −1.2 V

VOH VCC = MIN, VIL = 0.8 V, IOH = −1 mA 2.5 3.4 2.7 3.4 V

VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V



IIL VCC = MAX, VI = 0.5V −2 −2 mA

IOS§ VCC = MAX −40 −100 −40 −100 mA



† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time.


PARAMETERFROM

(INPUT)TO


SN54S00SN74S00 UNITPARAMETER


MIN TYP MAX


MIN TYP MAX


3 4.5ns


3 5ns


4.5ns


5ns

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PARAMETER MEASUREMENT INFORMATIONSERIES 54/74 DEVICES

tPHL tPLH

tPLH tPHL

LOAD CIRCUITFOR 3-STATE OUTPUTS

High-LevelPulse

Low-LevelPulse

VOLTAGE WAVEFORMSPULSE DURATIONS

Input

Out-of-PhaseOutput

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-PhaseOutput

(see Note D)

VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES

VCC

RL

Test Point

From OutputUnder Test

CL(see Note A)

LOAD CIRCUITFOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUITFOR 2-STATE TOTEM-POLE OUTPUTS

(see Note B)

VCC

RLFrom Output

Under Test

CL(see Note A)

TestPoint

(see Note B )

VCCRL


CL(see Note A)

TestPoint

1 kΩ

NOTES: A. CL includes probe and jig capacitance.B. All diodes are 1N3064 or equivalent.C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series

54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.F. The outputs are measured one at a time with one input transition per measurement.

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu

VOLTAGE WAVEFORMSSETUP AND HOLD TIMES

TimingInput

DataInput

3 V

0 V

OutputControl

(low-levelenabling)

Waveform 1(see Notes C

and D)


and D)≈1.5 V

VOH − 0.5 V

VOL + 0.5 V

≈1.5 V

VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

tw

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

VOH

VOL

Figure 1. Load Circuits and Voltage Waveforms

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SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004


Dependable Texas Instruments Quality andReliability

description/ordering informationThese devices contain six independent inverters.

Copyright 2004, Texas Instruments Incorporated


1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A1Y2A2Y3A3Y

GND

VCC6A6Y5A5Y4A4Y

SN5404 . . . J PACKAGESN54LS04, SN54S04 . . . J OR W PACKAGE

SN7404, SN74S04 . . . D, N, OR NS PACKAGESN74LS04 . . . D, DB, N, OR NS PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A2Y2A

VCC3A3Y4A

1Y6A6YGND5Y5A4Y

SN5404 . . . W PACKAGE(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

6YNC5ANC5Y

2ANC2YNC3A

SN54LS04, SN54S04 . . . FK PACKAGE(TOP VIEW)

1Y 1A NC

4Y 4A6A

3YG

ND

NC

NC − No internal connection

V CC

!" #!$% &"'&! #" #" (" " ") !"&& *+' &! #", &" ""%+ %!&"", %% #""'

#&! #% -./.010 %% #"" " ""&!%" ("*" "&' %% (" #&! #&!#", &" ""%+ %!&" ", %% #""'

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TOP-SIDEMARKING

Tube SN7404N SN7404N

PDIP − N Tube SN74LS04N SN74LS04NPDIP − N

Tube SN74S04N SN74S04N

Tube SN7404D7404

Tape and reel SN7404DR7404

SOIC − DTube SN74LS04D

LS040°C to 70°C

SOIC − DTape and reel SN74LS04DR

LS040 C to 70 C

Tube SN74S04DS04

Tape and reel SN74S04DRS04

Tape and reel SN7404NSR SN7404

SOP − NS Tape and reel SN74LS04NSR 74LS04SOP − NS

Tape and reel SN74S04NSR 74S04

SSOP − DB Tape and reel SN74LS04DBR LS04

Tube SN5404J SN5404J

Tube SNJ5404J SNJ5404J

CDIP − JTube SN54LS04J SN54LS04J

CDIP − JTube SN54S04J SN54S04J

Tube SNJ54LS04J SNJ54LS04J

−55°C to 125°C Tube SNJ54S04J SNJ54S04J−55 C to 125 C

Tube SNJ5404W SNJ5404W

CFP − W Tube SNJ54LS04W SNJ54LS04WCFP − W

Tube SNJ54S04W SNJ54S04W

LCCC − FKTube SNJ54LS04FK SNJ54LS04FK

LCCC − FKTube SNJ54S04FK SNJ54S04FK

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelinesare available at www.ti.com/sc/package.

FUNCTION TABLE(each inverter)

INPUTA

OUTPUTY

H L

L HElec

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logic diagram (positive logic)

1A

2A

3A

4A

5A

6A

1Y

2Y

3Y

4Y

5Y

6Y

Y = A

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schematics (each gate)

Input A

VCC

Output Y

GND

130 Ω

1 kΩ

1.6 kΩ

’04

4 kΩ

InputA

VCC

OutputY

GND

20 kΩ 120 Ω

’LS04

8 kΩ

12 kΩ

1.5 kΩ

3 kΩ

4 kΩ

InputA

VCC

Outpu tY

GND

2.8 kΩ900 Ω

’S04

50 Ω

3.5 kΩ

250 Ω

500 Ω

Resistor values shown are nominal.

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI: ’04, ’S04 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

’LS04 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.2. The package thermal impedance is calculated in accordance with JESD 51-7.


SN5404 SN7404SN5404 SN7404UNIT










PARAMETER TEST CONDITIONS‡SN5404 SN7404

UNITPARAMETER TEST CONDITIONS‡MIN TYP§ MAX MIN TYP§ MAX

UNIT

VIK VCC = MIN, II = −12 mA −1.5 −1.5 V

VOH VCC = MIN, VIL = 0.8 V, IOH = −0.4 mA 2.4 3.4 2.4 3.4 V

VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V



IIL VCC = MAX, VI = 0.4 V −1.6 −1.6 mA

IOS¶ VCC = MAX −20 −55 −18 −55 mA



‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.§ All typical values are at VCC = 5 V, TA = 25°C.¶ Not more than one output should be shorted at a time.

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PARAMETERFROM

(INPUT)TO

(OUTPUT) TEST CONDITIONS

SN5404SN7404 UNITPARAMETER (INPUT) (OUTPUT) TEST CONDITIONS

MIN TYP MAXUNIT

tPLHA Y RL = 400 Ω, CL = 15 pF

12 22ns

tPHLA Y RL = 400 Ω, CL = 15 pF

8 15ns


SN54LS04 SN74LS04SN54LS04 SN74LS04UNIT












UNIT

VIK VCC = MIN, II = −18 mA −1.5 −1.5 V

VOH VCC = MIN, VIL = MAX, IOH = −0.4 mA 2.5 3.4 2.7 3.4 V

VOL VCC = MIN, VIH = 2 VIOL = 4 mA 0.25 0.4 0.4

VVOL VCC = MIN, VIH = 2 VIOL = 8 mA 0.25 0.5

V

II VCC = MAX, VI = 7 V 0.1 0.1 mA


IIL VCC = MAX, VI = 0.4 V −0.4 −0.4 mA

IOS§ VCC = MAX −20 −100 −20 −100 mA

ICCH VCC = MAX, VI = 0 V 1.2 2.4 1.2 2.4 mA

ICCL VCC = MAX, VI = 4.5 V 3.6 6.6 3.6 6.6 mA

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.


PARAMETERFROM

(INPUT)TO


SN54LS04SN74LS04 UNITPARAMETER (INPUT) (OUTPUT) TEST CONDITIONS

MIN TYP MAXUNIT

tPLHA Y RL = 2 kΩ, CL = 15 pF

9 15ns

tPHLA Y RL = 2 kΩ, CL = 15 pF

10 15ns

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SN54S04 SN74S04SN54S04 SN74S04UNIT










PARAMETER TEST CONDITIONS†SN54S04 SN74S04


UNIT

VIK VCC = MIN, II = −18 mA −1.2 −1.2 V

VOH VCC = MIN, VIL = 0.8 V, IOH = −1 mA 2.5 3.4 2.7 3.4 V

VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V



IIL VCC = MAX, VI = 0.5 V −2 −2 mA

IOS§ VCC = MAX −40 −100 −40 −100 mA



† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.


PARAMETERFROM

(INPUT)TO


SN54S04SN74S04 UNITPARAMETER (INPUT) (OUTPUT) TEST CONDITIONS

MIN TYP MAXUNIT


3 4.5ns


3 5ns


4.5ns


5nsEl

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PARAMETER MEASUREMENT INFORMATIONSERIES 54/74 AND 54S/74S DEVICES

tPHL tPLH

tPLH tPHL


High-LevelPulse

Low-LevelPulse


Input

Out-of-PhaseOutput

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-PhaseOutput

(see Note D)


VCC

RL

Test Point


CL(see Note A)



(see Note B)

VCC

RLFrom Output

Under Test

CL(see Note A)

TestPoint

(see Note B )

VCCRL


CL(see Note A)

TestPoint

1 kΩ

NOTES: A. CL includes probe and jig capacitance.B. All diodes are 1N3064 or equivalent.C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series

54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.F. The outputs are measured one at a time, with one input transition per measurement.

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu


TimingInput

DataInput

3 V

0 V

OutputControl

(low-levelenabling)


and D)


and D)≈1.5 V

VOH − 0.5 V

VOL + 0.5 V

≈1.5 V


1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

tw

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

VOH

VOL


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PARAMETER MEASUREMENT INFORMATIONSERIES 54LS/74LS DEVICES

tPHL tPLH

tPLH tPHL


High-LevelPulse

Low-LevelPulse


Input

Out-of-PhaseOutput

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-PhaseOutput

(see Note D)


VCC

RL

Test Point


CL(see Note A)



(see Note B)

VCC

RLFrom Output

Under Test

CL(see Note A)

TestPoint

(see Note B )

VCCRL


CL(see Note A)

TestPoint

5 kΩ

NOTES: A. CL includes probe and jig capacitance.B. All diodes are 1N3064 or equivalent.C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.G. The outputs are measured one at a time, with one input transition per measurement.

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu


TimingInput

DataInput

3 V

0 V

OutputControl

(low-levelenabling)


and D)


and D) ≈1.5 V

VOH − 0.5 V

VOL + 0.5 V

≈1.5 V


1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

tw

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

VOL

VOH


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SN5408, SN54LS08, SN54S08SN7408, SN74LS08, SN74S08QUADRUPLE 2-INPUT POSITIVE-AND GATESSDLS033 – DECEMBER 1983 – REVISED MARCH 1988


Copyright 1988, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

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Semiconductor Components Industries, LLC, 2011

May, 2011 Rev. 51 Publication Order Number:

MC74VHC86/D

MC74VHC86

Quad 2-Input XOR GateThe MC74VHC86 is an advanced high speed CMOS 2 input

Exclusive OR gate fabricated with silicon gate CMOS technology. It

achieves high speed operation similar to equivalent Bipolar Schottky

TTL while maintaining CMOS low power dissipation.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7 V, allowing the interface of 5 V

systems to 3 V systems.

Features

• High Speed: tPD = 4.8 ns (Typ) at VCC = 5 V

• Low Power Dissipation: ICC = 2 A (Max) at TA = 25°C

• High Noise Immunity: VNIH = VNIL = 28% VCC

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Designed for 2 V to 5.5 V Operating Range

• Low Noise: VOLP = 0.8 V (Max)

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300 mA

• ESD Performance: Human Body Model (HBM) > 2000 V;

Machine Model > 200 V

• Chip Complexity: 56 FETs or 14 Equivalent Gates

• These Devices are Pb Free and are RoHS Compliant

Figure 1. Logic Diagram

Y = AB

3Y1

1A1

2B1

6Y2

4A2

5B2

8Y3

9A3

10B3

11Y4

12A4

13B4

Figure 2. Pinout: 14 Lead Packages (Top View)

1314 12 11 10 9 8

21 3 4 5 6 7

VCC B4 A4 Y4 B3 A3 Y3

A1 B1 Y1 A2 B2 Y2 GND

MARKING

DIAGRAMS

TSSOP 14DT SUFFIXCASE 948G1

SOEIAJ 14M SUFFIXCASE 965

SOIC 14D SUFFIX

CASE 751A

1

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.


http://onsemi.com

A = Assembly Location

WL, L = Wafer Lot

Y, YY = Year

WW, W = Work Week

G or = Pb Free Package

1

14

VHC86

ALYWG

VHC86G

AWLYWW

1

14

VHC86

ALYW

1

14

(Note: Microdot may be in either location)

1

14

Inputs Output

FUNCTION TABLE

A B Y

L

L

H

H

L

H

L

H

L

H

H

L

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MC74VHC86

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter ÎÎÎÎÎÎÎÎÎÎ

Value ÎÎÎÎÎÎ

Unit

ÎÎÎÎÎÎÎÎ

VCCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage ÎÎÎÎÎÎÎÎÎÎ

–0.5 to +7.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

VinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage ÎÎÎÎÎÎÎÎÎÎ

–0.5 to +7.0ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

VoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage ÎÎÎÎÎÎÎÎÎÎ

–0.5 to VCC +0.5ÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎ

IIKÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Diode Current ÎÎÎÎÎÎÎÎÎÎ

20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ

IOKÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Diode Current ÎÎÎÎÎÎÎÎÎÎ

20 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ

IoutÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin ÎÎÎÎÎÎÎÎÎÎ

25 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎ

ICCÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins ÎÎÎÎÎÎÎÎÎÎ

50 ÎÎÎÎÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎ

PDÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, SOIC Packages†

TSSOP Package†

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

500450

ÎÎÎÎÎÎÎÎÎ

mW

ÎÎÎÎÎÎÎÎ

Tstg ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature ÎÎÎÎÎÎÎÎÎÎ

–65 to +150ÎÎÎÎÎÎ

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stressratings only. Functional operation above the Recommended Operating Conditions is not implied.Extended exposure to stresses above the Recommended Operating Conditions may affect devicereliability.†Derating SOIC Packages: – 7 mW/°C from 65° to 125°C

TSSOP Package: 6.1 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONSÎÎÎÎÎÎÎÎ

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ParameterÎÎÎÎÎÎÎÎÎÎ

MinÎÎÎÎÎÎÎÎÎÎ

MaxÎÎÎÎÎÎÎÎ

UnitÎÎÎÎÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply VoltageÎÎÎÎÎÎÎÎÎÎ

2.0ÎÎÎÎÎÎÎÎÎÎ

5.5ÎÎÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ

Vin


DC Input VoltageÎÎÎÎÎÎÎÎÎÎ

0ÎÎÎÎÎÎÎÎÎÎ

5.5ÎÎÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ

Vout


DC Output VoltageÎÎÎÎÎÎÎÎÎÎ


VCC

ÎÎÎÎÎÎÎÎ

VÎÎÎÎÎÎÎÎ

TA


Operating Temperature, All Package TypesÎÎÎÎÎÎÎÎÎÎ


+125ÎÎÎÎÎÎÎÎ

°CÎÎÎÎÎÎÎÎÎÎÎÎ

tr, tfÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 3.3 V ±0.3 V

VCC = 5.0 V ±0.5 V


00


10020


ns/V

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND (Vin or Vout) VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

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MC74VHC86

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS


Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter


Test Conditions

ÎÎÎÎÎÎÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

TA = 25°C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

TA = 55°C to +125°CÎÎÎÎÎÎÎÎÎ


Min ÎÎÎÎÎÎ

TypÎÎÎÎÎÎÎÎ

Max ÎÎÎÎÎÎÎÎ

Min ÎÎÎÎÎÎÎÎ

Max


VIHÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

High Level Input

Voltage


ÎÎÎÎÎÎÎÎÎ

2.03.0 to5.5


1.50VCC x 0.7

ÎÎÎÎÎÎÎÎÎ



1.50VCC x 0.7


ÎÎÎÎÎÎÎÎÎ

V


VIL


Low Level Input

Voltage


ÎÎÎÎÎÎÎÎÎ

2.03.0 to5.5


ÎÎÎÎÎÎÎÎÎ


0.50VCC x 0.3



0.50VCC x 0.3

ÎÎÎÎÎÎÎÎÎ

V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

High Level Output

Voltage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

IOH = 50 A


2.03.04.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

1.92.94.4


2.03.04.5



1.92.94.4



V


Vin = VIH or VIL

IOH = 4 mA

IOH = 8 mA

ÎÎÎÎÎÎÎÎÎ

3.04.5


2.583.94

ÎÎÎÎÎÎÎÎÎ



2.483.80



VOL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Low Level Output

Voltage


Vin = VIH or VIL

IOL = 50 A

ÎÎÎÎÎÎÎÎÎ

2.03.04.5


ÎÎÎÎÎÎÎÎÎ

000


0.10.10.1



0.10.10.1


V


Vin = VIH or VIL

IOL = 4 mA

IOL = 8 mA

ÎÎÎÎÎÎÎÎÎ

3.04.5


ÎÎÎÎÎÎÎÎÎ


0.360.36



0.440.44

ÎÎÎÎÎÎÎÎIin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Leakage Current

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin = 5.5 V or GND

ÎÎÎÎÎÎ0 to 5.5ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ±0.1

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ±1.0

ÎÎÎÎÎÎAÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ICC


Quiescent Supply

Current


Vin = VCC or GNDÎÎÎÎÎÎÎÎÎ

5.5ÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ


2.0ÎÎÎÎÎÎÎÎÎÎÎÎ


20.0ÎÎÎÎÎÎÎÎÎ

A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)


Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

TA = 25°C


TA = 55°C to

+125°C

ÎÎÎÎÎÎÎÎ


Min ÎÎÎÎÎÎ

TypÎÎÎÎÎÎÎÎ

Max ÎÎÎÎÎÎ

MinÎÎÎÎÎÎÎÎ

Max


tPLH,tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay, A or B to YÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3 V CL = 15 pF

CL = 50 pF


ÎÎÎÎÎÎÎÎÎ

7.09.5ÎÎÎÎÎÎÎÎÎÎÎÎ

11.014.5ÎÎÎÎÎÎÎÎÎ

1.01.0ÎÎÎÎÎÎÎÎÎÎÎÎ

13.016.5ÎÎÎÎÎÎÎÎ

ns


VCC = 5.0 ± 0.5 V CL = 15 pF

CL = 50 pFÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ


6.88.8ÎÎÎÎÎÎ


8.010.0

ÎÎÎÎÎÎÎÎ

CinÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input CapacitanceÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

4ÎÎÎÎÎÎÎÎ

10ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

10ÎÎÎÎ

pF

CPD Power Dissipation Capacitance (Note 1.)

Typical @ 25°C, VCC = 5.0 V

pF18

1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine theno load dynamic power consumption; PD = CPD VCC

2 fin + ICC VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0 V, Measured in SOIC Package)

Symbol Characteristic

TA = 25°C

UnitTyp Max

VOLP Quiet Output Maximum Dynamic VOL 0.3 0.8 V

VOLV Quiet Output Minimum Dynamic VOL 0.3 0.8 V

VIHD Minimum High Level Dynamic Input Voltage 3.5 V

VILD Maximum Low Level Dynamic Input Voltage 1.5 V

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MC74VHC86

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Device Package Shipping†

MC74VHC86DR2G SOIC 14(Pb Free)

2500 Tape & Reel

MC74VHC86DTG TSSOP 14(Pb Free)

96 Units / Rail

MC74VHC86DTR2G TSSOP 14(Pb Free)

2500 Tape & Reel

MC74VHC86MELG SOEIAJ 14(Pb Free)

2000 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

Figure 3. Switching Waveforms

VCC

GND

50%

50% VCC

A or B

Y

tPHLtPLH

*Includes all probe and jig capacitance

Figure 4. Test Circuit

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 5. Input Equivalent Circuit

INPUT

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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTSSDLS144C − APRIL 1985 − REVISED MAY 2010


3-State Outputs Drive Bus Lines or Buffer

Memory Address Registers

PNP Inputs Reduce DC Loading

Hysteresis at Inputs Improves Noise

Margins

description

These octal buffers and line drivers are designedspecifically to improve both the performance anddensity of three-state memory address drivers,clock drivers, and bus-oriented receivers andtransmitters. The designer has a choice ofselected combinations of inverting andnoninverting outputs, symmetrical, active-lowoutput-control (G) inputs, and complementaryoutput-control (G and G) inputs. These devicesfeature high fan-out, improved fan-in, and 400-mVnoise margin. The SN74LS’ and SN74S’ devicescan be used to drive terminated lines down to133 Ω.


Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

1G

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

VCC

2G/2G†

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1

SN54LS’, SN54S’ . . . J OR W PACKAGE

SN74LS240, SN74LS244 . . . DB, DW, N, OR NS PACKAGE

SN74LS241 . . . DW, N, OR NS PACKAGE

SN74S’ . . . DW OR N PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

1Y1

2A4

1Y2

2A3

1Y3

1A2

2Y3

1A3

2Y2

1A4

SN54LS’, SN54S’ . . . FK PACKAGE

(TOP VIEW)

2Y

4

1A

1

1G

1Y

4

2A

22G

/2G

2Y

1

GN

D

2A

1V

CC

† 2G for ’LS241 and ’S241 or 2G for all other drivers.

† 2G for ’LS241 and ’S241 or 2G for all other drivers.

†

On products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.

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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTSSDLS144C − APRIL 1985 − REVISED MAY 2010



TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING

SN74LS240N SN74LS240N

SN74LS241N SN74LS241N

PDIP N TubeSN74LS244N SN74LS244N

PDIP − N TubeSN74S240N SN74S240N

SN74S241N SN74S241N

SN74S244N SN74S244N

Tube SN74LS240DWLS240

Tape and reel SN74LS240DWRLS240




0°C to 70°CSOIC DW


SOIC − DWTube SN74S240DW

S240Tape and reel SN74S240DWR

S240

Tube SN74S241DWS241

Tape and reel SN74S241DWRS241

Tube SN74S244DWS244


SN74LS240NSR 74LS240

SOP − NS Tape and reel SN74LS241NSR 74LS241SOP NS Tape and reel

SN74LS244NSR 74LS244

SSOP DB Tape and reelSN74LS240DBR LS240

SSOP − DB Tape and reelSN74LS244DBR LS244

† For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site

at www.ti.com.‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

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ORDERING INFORMATION (CONTINUED)

TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING

SN54LS240J SN54LS240J

SNJ54LS240J SNJ54LS240J


SNJ54LS241J SNJ54LS241J


CDIP J TubeSNJ54LS244J SNJ54LS244J

CDIP − J TubeSN54S240J SN54S240J

SNJ54S240J SNJ54S240J

SN54S241J SN54S241J

SNJ54S241J SNJ54S241J

SN54S244J SN54S244J

55°C to 125°CSNJ54S244J SNJ54S244J

−55°C to 125°CSNJ54LS240W SNJ54LS240W

SNJ54LS241W SNJ54LS241W

CFP W TubeSNJ54LS244W SNJ54LS244W

CFP − W TubeSNJ54S240W SNJ54S240W

SNJ54S241W SNJ54S241W

SNJ54S244W SNJ54S244W

SNJ54LS240FK SNJ54LS240FK

SNJ54LS241FK SNJ54LS241FK

LCCC FK TubeSNJ54LS244FK SNJ54LS244FK

LCCC − FK TubeSNJ54S240FK SNJ54S240FK

SNJ54S241FK SNJ54S241FK

SNJ54S244FK SNJ54S244FK

† For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site

at www.ti.com.‡ Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

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schematics of inputs and outputs

R

VCC

Output

TYPICAL OF ALL OUTPUTS

Req

VCC

Input

EQUIVALENT OF EACH INPUTEQUIVALENT OF EACH INPUT

9 kΩ NOM

Input

VCC

’LS240. ’LS241, ’LS244: R = 50 Ω NOM

’S240, ‘S241, S244: R = 25 Ω NOM

GND

G and G inputs: Req = 2 kΩ NOM

A inputs: Req = 2.8 kΩ NOM

’LS240, ’LS241, ’LS244 ’S240, ’S241, ’S244

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logic diagram

1

2

4

6

8

19

11

13

15

17 3

5

7

9

12

14

16

181A1

1A2

1A3

1A4

1Y1

2A1

2A2

2A3

2A4

2Y1

1Y2

1Y3

1Y4

2Y2

2Y3

2Y4

2G

1G

’LS240, ’S240 ’LS241, ’S241

’LS244, ’S244

1

2

4

6

8

19

11

13

15

17 3

5

7

9

12

14

16

181A1

1A2

1A3

1A4

1Y1

2A1

2A2

2A3

2A4

2Y1

1Y2

1Y3

1Y4

2Y2

2Y3

2Y4

2G

1G

1

2

4

6

8

19

11

13

15

17 3

5

7

9

12

14

16

181A1

1A2

1A3

1A4

1Y1

2A1

2A2

2A3

2A4

2Y1

1Y2

1Y3

1Y4

2Y2

2Y3

2Y4

2G

1G

Pin numbers shown are for DB, DW, J, N, NS, and W packages.

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI: ’LS 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

’S 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-state output voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

SN54LS’ SN74LS’UNIT


VCC Supply voltage (see Note 1) 4.5 5 5.5 4.75 5 5.25 V






NOTE 1: Voltage values are with respect to network ground terminal.

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PARAMETER TEST CONDITIONS†SN54LS’ SN74LS’

UNITPARAMETER TEST CONDITIONS†

MIN TYP‡ MAX MIN TYP‡ MAXUNIT

VIK VCC = MIN, II = −18 mA −1.5 −1.5 V

Hysteresis

(VT+ − VT−)VCC = MIN 0.2 0.4 0.2 0.4 V

V

VCC = MIN,

IOH = −3 mAVIH = 2 V, VIL = MAX, 2.4 3.4 2.4 3.4

VVOHVCC = MIN,

IOH = MAXVIH = 2 V, VIL = 0.5 V, 2 2

V

VVCC = MIN,

V 2 VIOL = 12 mA 0.4 0.4

VVOLVCC = MIN,

VIL = MAXVIH = 2 V,

IOL = 24 mA 0.5V

IOZHVCC = MAX,

VIL = MAXVIH = 2 V, VO = 2.7 V 20 20 µA

IOZLVCC = MAX,

VIL = MAXVIH = 2 V, VO = 0.4 V −20 −20 µA

II VCC = MAX, VI = 7 V 0.1 0.1 mA


IIL VCC = MAX, VIL = 0.4 V −0.2 −0.2 mA

IOS§ VCC = MAX, −40 −225 −40 −225 mA

Outputs high All 17 27 17 27

V MAX Outputs low’LS240 26 44 26 44

ICCVCC = MAX,

Output open

Outputs low’LS241, ’LS244 27 46 27 46 mAICC Output open

Outputs disabled’LS240 29 50 29 50

mA

Outputs disabled’LS241, ’LS244 32 54 32 54

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

PARAMETER TEST CONDITIONS’LS240 ’LS241, ’LS244

UNITPARAMETER TEST CONDITIONSMIN TYP MAX MIN TYP MAX

UNIT

tPLHR 667 Ω C 45 pF

9 14 12 18ns

tPHLRL = 667 Ω, CL = 45 pF

12 18 12 18ns

tPZLR 667 Ω C 45 F

20 30 20 30ns

tPZHRL = 667 Ω, CL = 45 pF

15 23 15 23ns

tPLZR 667 Ω C 5 pF

10 20 10 20ns

tPHZ

RL = 667 Ω, CL = 5 pF15 25 15 25

ns

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SN54S’ SN74S’UNIT


VCC Supply voltage (see Note 1) 4.5 5 5.5 4.75 5 5.25 V





External resistance between any input and VCC or ground 40 40 kΩ

TA Operating free-air temperature (see Note 3) −55 125 0 70 °C

NOTES: 1. Voltage values are with respect to network ground terminal.

3. An SN54S241J operating at free-air temperature above 116°C requires a heat sink that provides a thermal resistance from case

to free air, RθCA, of not more that 40°C/W.


PARAMETER TEST CONDITIONS†SN54S’ SN74S’

UNITPARAMETER TEST CONDITIONS†

MIN TYP‡ MAX MIN TYP‡ MAXUNIT

VIK VCC = MIN, II = −18 mA −1.2 −1.2 V

Hysteresis

(VT+ − VT−)VCC = MIN 0.2 0.4 0.2 0.4 V

VCC = MIN

IOH = −1 mA

VIH = 2 V, VIL = 0.8 V,2.7

VOHVCC = MIN,

IOH = −3 mA

VIH = 2 V, VIL = 0.8 V,2.4 3.4 2.4 3.4 V

VCC = MIN,

IOH = MAX

VIH = 2 V, VIL = 0.5 V,2 2

VOLVCC = MIN,

IOL = MAX

VIH = 2 V, VIL = 0.8 V,0.55 0.55 V

IOZHVCC = MAX,

VIL = 0.8 V

VIH = 2 V,VO = 2.4 V 50 50 µA

IOZLVCC = MAX,

VIL = 0.8 V

VIH = 2 V,VO = 0.5 V −50 −50 µA



I V MAX V 0 5 VAny A −400 −400 µA

IIL VCC = MAX, VI = 0.5 VAny G −2 −2 mA

IOS§ VCC = MAX −50 −225 −50 −225 mA

Outputs high’S240 80 123 80 135

Outputs high’S241,’S244 95 147 95 160

IVCC = MAX,

Outputs low’S240 100 145 100 150

mAICCVCC = MAX,

Output openOutputs low

’S241, ’S244 120 170 120 180mA

Outputs disabled’S240 100 145 100 150

Outputs disabled’S241, ’S244 120 170 120 180

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

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switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2)

PARAMETER TEST CONDITIONS’S240 ’S241, ’S244

UNITPARAMETER TEST CONDITIONSMIN TYP MAX MIN TYP MAX

UNIT

tPLHR 90 Ω C 50 F

4.5 7 6 9ns

tPHLRL = 90 Ω, CL = 50 pF

4.5 7 6 9ns

tPZLR 90 Ω C 50 F

10 15 10 15ns

tPZHRL = 90 Ω, CL = 50 pF

6.5 10 8 12ns

tPLZR 90 Ω C 5 pF

10 15 10 15ns

tPHZ

RL = 90 Ω, CL = 5 pF6 9 6 9

ns

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tPHL tPLH

tPLH tPHL

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

High-Level

Pulse

Low-Level

Pulse

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

Out-of-Phase

Output

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-Phase

Output

(see Note D)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC

RL

Test

Point

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS

(see Note B)

VCC

RL

From Output

Under Test

CL

(see Note A)

Test

Point

(see Note B)

VCC

RL

From Output

Under Test

CL

(see Note A)

Test

Point

5 kΩ

NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.

E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.

F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 15 ns, tf ≤ 6 ns.

G. The outputs are measured one at a time with one input transition per measurement.

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data

Input

3 V

0 V

Output

Control

(low-level

enabling)

Waveform 1

(see Notes C

and D)

Waveform 2

(see Notes C

and D) ≈1.5 V

VOH − 0.3 V

VOL + 0.3 V

≈1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

tw

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

VOL

VOH


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PARAMETER MEASUREMENT INFORMATIONSERIES 54S/74S DEVICES

tPHL tPLH

tPLH tPHL

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

High-Level

Pulse

Low-Level

Pulse

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

Out-of-Phase

Output

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-Phase

Output

(see Note D)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC

RL

Test

Point

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS

(see Note B)

VCC

RL

From Output

Under Test

CL

(see Note A)

Test

Point

(see Note B)

VCC

RL

From Output

Under Test

CL

(see Note A)

Test

Point

1 kΩ

NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.

E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series

54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.

F. The outputs are measured one at a time with one input transition per measurement.

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data

Input

3 V

0 V

Output

Control

(low-level

enabling)

Waveform 1

(see Notes C

and D)

Waveform 2

(see Notes C

and D)≈1.5 V

VOH − 0.5 V

VOL + 0.5 V

≈1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

tw

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

VOH

VOL


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APPLICATION INFORMATIONEl

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SN54LS245, SN74LS245OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTSSDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002


3-State Outputs Drive Bus Lines Directly

PNP Inputs Reduce dc Loading on BusLines

Hysteresis at Bus Inputs Improves NoiseMargins

Typical Propagation Delay Times Port toPort, 8 ns

TYPEIOL

(SINKCURRENT)

IOH(SOURCE

CURRENT)

SN54LS245 12 mA –12 mA

SN74LS245 24 mA –15 mA

description

These octal bus transceivers are designed forasynchronous two-way communication betweendata buses. The control-function implementationminimizes external timing requirements.

The devices allow data transmission from theA bus to the B bus or from the B bus to the A bus,depending on the logic level at thedirection-control (DIR) input. The output-enable(OE) input can disable the device so that thebuses are effectively isolated.



TOP-SIDEMARKING

PDIP – N Tube SN74LS245N SN74LS245N

SOIC – DWTube SN74LS245DW

LS2450°C to 70°C

SOIC – DWTape and reel SN74LS245DWR

LS245

SOP – NS Tape and reel SN74LS245NSR 74LS245

SSOP – DB Tape and reel SN74LS245DBR LS245

CDIP – JTube SN54LS245J SN54LS245J

–55°C to 125°C

CDIP – JTube SNJ54LS245J SNJ54LS245J

–55°C to 125°CCFP – W Tube SNJ54LS245W SNJ54LS245W

LCCC – FK Tube SN54LS245FK SN54LS245FK

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB designguidelines are available at www.ti.com/sc/package.



3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

B1B2B3B4B5

A3A4A5A6A7

A2

A1

DIR

B7

B6

OE

A8

GN

D B8

VC

C

SN54LS245 . . . FK PACKAGE(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

DIRA1A2A3A4A5A6A7A8

GND

VCCOEB1B2B3B4B5B6B7B8

SN54LS245 . . . J OR W PACKAGESN74LS245 . . . DB, DW, N, OR NS PACKAGE

(TOP VIEW)


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SN54LS245, SN74LS245OCTAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002


FUNCTION TABLE

INPUTSOPERATION

OE DIROPERATION

L L B data to A bus

L H A data to B bus

H X Isolation

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT

VCC

Input

9 kΩ NOM


Output

VCC

50 Ω NOM


DIR

OE

A1

B1

1

2

18

19

To Seven Other Channels

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †

Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, JA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


NOTES: 1. All voltage values are with respect to GND.2. The package thermal impedance is calculated in accordance with JESD 51-7.


SN54LS245 SN74LS245UNIT



IOH High-level output current –12 –15 mA


TA Operating free-air temperature –55 125 0 70 °C

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SN54LS245, SN74LS245OCTAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTSSDLS146A – OCTOBER 1976 – REVISED FEBRUARY 2002





UNIT



VIK Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V

Hysteresis (VT+ – VT–) A or B VCC = MIN 0.2 0.4 0.2 0.4 V

VOH High level output voltageVCC = MIN,VIH 2 V

IOH = –3 mA 2.4 3.4 2.4 3.4VVOH High-level output voltage VIH = 2 V,

VIL = VIL(max) IOH = MAX 2 2V

VOL Low level output voltageVCC = MIN,VIH 2 V

IOL = 12 mA 0.4 0.4VVOL Low-level output voltage VIH = 2 V,

VIL = VIL(max) IOL = 24 mA 0.5V

IOZHOff-state output current,high-level voltage applied

VCC = MAX,OE at 2 V

VO = 2.7 V 20 20 µA

IOZLOff-state output current,low-level voltage applied

VCC = MAX,OE at 2 V

VO = 0.4 V –200 –200 µA

II

Input current atmaximum input

A or BVCC = MAX

VI = 5.5 V 0.1 0.1mAII maximum input

voltage DIR or OEVCC = MAX

VI = 7 V 0.1 0.1mA

IIH High-level input current VCC = MAX, VIH = 2.7 V 20 20 µA

IIL Low-level input current VCC = MAX, VIL = 0.4 V –0.2 –0.2 mA

IOS Short-circuit output current§ VCC = MAX –40 –225 40 –225 mA

Total, outputs high 48 70 48 70

ICC Supply current Total, outputs low VCC = MAX Outputs open 62 90 62 90 mA

Outputs at high Z 64 95 64 95

† For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.


PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tPLH Propagation delay time, low- to high-level outputC 45 pF R 667

8 12ns

tPHL Propagation delay time high to low level outputCL = 45 pF, RL = 667

8 12ns

tPHL Propagation delay time, high- to low-level output 8 12

tPZL Output enable time to low levelCL = 45 pF RL = 667

27 40ns

tPZH Output enable time to high levelCL = 45 pF, RL = 667

25 40ns

tPLZ Output disable time from low levelCL = 5 pF RL = 667

15 25ns

tPHZ Output disable time from high levelCL = 5 pF, RL = 667

15 28ns

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tPHL tPLH

tPLH tPHL


High-LevelPulse

Low-LevelPulse


Input

Out-of-PhaseOutput

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-PhaseOutput

(see Note D)


VCC

RL

Test Point


CL(see Note A)



(see Note B)

VCC

RLFrom Output

Under Test

CL(see Note A)

TestPoint

(see Note B)

VCCRL


CL(see Note A)

TestPoint

5 kΩ


Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.G. The outputs are measured one at a time with one input transition per measurement.

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu


TimingInput

DataInput

3 V

0 V

OutputControl

(low-levelenabling)


and D)


and D) ≈1.5 V

VOH – 0.5 V

VOL + 0.5 V

≈1.5 V


1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

tw

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

VOL

VOH


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Capítulo 3.- Dispositivos combinacionales

3.1.- Decodificador . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2

3.2.- Selector/multiplexor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3

3.3.- Referencias del capítulo 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5

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Figura 3.1. Esquema digital del circuito 74LS138.

Capítulo 3.- Dispositivos combinacionalesUn circuito combinacional es aquel en el que el estado de sus salidas depende

únicamente del estado de sus entradas y sus combinaciones. Todos los elementosbásicos vistos en el apartado anterior entran dentro de este grupo de dispositivos.

La forma de identificar un circuito combinacional es por medio de su nombre (sies un circuito típico) o por medio de su tabla de verdad. También es posible hacerlo pormedio de su cronograma, pero no es lo más habitual.

Hay una colección de circuitos típicos que se utilizan habitualmente y que seidentifican simplemente por medio de su nombre. A continuación vemos algunos deellos. En muchos casos hacemos uso de modelos industriales reales cuyadocumentación se adjunta para contrastar los detalles.

3.1.- Decodificador

Un decodificador es un circuito combinacional que sirve para identificar un códigoo para identificar un valor numérico. La figura 3.1 muestra el esquema lógico de undecodificador comercial (74 LS138) que se denomina decodificador 3 a 8 porquedispone de tres entradas y ocho salidas y su funcionamiento es de tal forma que paracada una de las 8 posibles combinaciones de las señales binarias de entrada (23 =8),se activa una y solo una señal de salida. La figura 3.2 es la tabla de verdadcorrespondiente al esquema de la figura 3.1.

Como puede verse en la figura 3.1, el dispositivo tiene en total seis señales deentrada, tres de ellas se denominan E (Enable, /E1, /E2 y E3), las otras tres señales sedenominan A (A0, A1 y A2). Las entradas E son las de habilitación y sirven paracontrolar el funcionamiento del dispositivo. Funcionan de forma que si no tienen el

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Figura 3.2. Tabla de verdad del circuito 74LS138.

Figura 3.3. Selector/multiplexor de 2 a 1, símbolo y tablade verdad

C S

0 E0

1 E1

estado especificado en la tabla de verdad, el circuito no produce ninguna salida. Estocorresponde a las tres primeras filas de la tabla. Cuando estas señales tienen el estado/E1 = L, /E2 = L y E3 = H, el circuito funciona como se describe en la tabla, haciendo queuna de las 8 salidas se active según sea la combinación de los estados de las señalesA. Observar que la activación de las señales de salida es a nivel bajo.

Este dispositivo realiza una decodificación de un código octal en representaciónbinaria a octal en representación decimal.


3.2.- Selector/multiplexor

Como su nombre indica, un selector es un circuito que permite seleccionar entrevarias opciones. En nuestro caso permite seleccionar entre varias señales, es decirdispone de varias señales de entradas entre las cuales seleccionamos una para quesea igual que la salida. La figura 3.3 muestra el esquema digital de un selector de dosentradas y una salida y su símbolo.

La tabla de verdad de este dispositivo es la mostrada en la tabla de la figura 3.3.La señal de control C nos permite hacer que a la salida S tengamos la señal E0

o la señal E1. Esto es lo que se ha representado en el cronograma de la figura 3.4.

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Figura 3.4.Cronograma ejemplode funcionamiento deun selector 2-1.

Figura 3.5. Selector/multiplexor de 4 a 1. Tabla de verdad,esquema y símbolo.

C1 C0 Salida

H L E0

H H E1

L L E2

L H E3

La figura 3.5 muestra el esquema lógico y el símbolo de un selector 4-1. En estecaso disponemos de dos señales de control cuyas combinaciones binarias realizan laselección de la señal de entrada a la salida. La tabla de verdad que describe sufuncionamiento es:

La referencia DM74150 es un selector/multiplexor de 16 entradas, para lo cual sonnecesarias 4 señales de control.El

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DM74150, DM74151AData Selectors/MultiplexersGeneral DescriptionThese data selectors/multiplexers contain full on-chip decod-ing to select the desired data source. The 150 selectsone-of-sixteen data sources; the 151A selects one-of-eightdata sources. The 150 and 151A have a strobe input whichmust be at a low logic level to enable these devices. A highlevel at the strobe forces the W output high and the Y output(as applicable) low.

The 151A features complementary W and Y outputs,whereas the 150 has an inverted (W) output only.

The 151A incorporates address buffers which have sym-metrical propagation delay times through the complementarypaths. This reduces the possibility of transients occurring atthe output(s) due to changes made at the select inputs, evenwhen the 151A outputs are enabled (i.e., strobe low).

Featuresn 150 selects one-of-sixteen data linesn 151A selects one-of-eight data linesn Performs parallel-to-serial conversionn Permits multiplexing from N lines to one linen Also for use as Boolean function generatorn Typical average propagation delay time, data input to W

output150 11 ns151A 9 ns

n Typical power dissipation150 200 mW151A 135 mW

n Alternate Military/Aerospace device (54150, 54151A) isavailable. Contact a Fairchild Semiconductor SalesOffice/Distributor for specifications.

Connection Diagrams

Dual-In-Line Package

DS006546-1

Order Number 54150DQMB, 54150FMQB,DM54150J or DM74150N

See Package Number J24A, N24A or W24C

Dual-In-Line Package

DS006546-2

Order Number 54151ADMQB, 54151AFMQB,DM54151AJ, DM54151AW or DM74151AN

See Package Number J16A, N16E or W16A

March 1998

DM

74150,DM

74151AD

ataS

electors/Multiplexers

© 1998 Fairchild Semiconductor Corporation DS006546 www.fairchildsemi.com

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Absolute Maximum Ratings (Note 1)

Supply Voltage 7VInput Voltage 5.5VOperating Free Air Temperature Range

DM54 and 54 −55˚C to +125˚CDM74 0˚C to +70˚C

Storage Temperature Range −65˚C to +150˚C

Recommended Operating Conditions

Symbol Parameter DM54150 DM74150 Units

Min Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.8 0.8 V

IOH High Level Output Current −0.8 −0.8 mA

IOL Low Level Output Current 16 16 mA

TA Free Air Operating Temperature −55 125 0 70 ˚CNote 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at theselimits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended OperatingConditions” table will define the conditions for actual device operation.

’150 Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 2)

VI Input Clamp Voltage VCC = Min, II = −12 mA −1.5 V

VOH High Level Output VCC = Min, IOH = Max 2.4 V

Voltage VIL = Max, VIH = Min

VOL Low Level Output VCC = Min, IOL = Max 0.4 V

Voltage VIH = Min, VIL = Max

II Input Current @ Max VCC = Max, VI = 5.5V 1 mA

Input Voltage

IIH High Level Input Current VCC = Max, VI = 2.4V 40 µA

IIL Low Level Input Current VCC = Max, VI = 0.4V −1.6 mA

IOS Short Circuit VCC = Max DM54 −20 −55 mA

Output Current (Note 3) DM74 −18 −55

ICC Supply Current VCC = Max, (Note 4) 40 68 mA

Note 2: All typicals are at VCC = 5V, TA = 25˚C.

Note 3: Not more than one output should be shorted at a time.

Note 4: ICC is measured with the strobe and data select inputs at 4.5V, all other inputs and outputs open.

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’150 Switching Characteristicsat VCC = 5V and TA = 25˚C

Symbol Parameter From (Input) RL = 400Ω, CL = 15 pF Units

To (Output) Min Max

tPLH Propagation Delay Time Select 35 ns

Low to High Level Output to W

tPHL Propagation Delay Time Select 33 ns

High to Low Level Output to W

tPLH Propagation Delay Time Strobe 24 ns


tPHL Propagation Delay Time Strobe 30 ns


tPLH Propagation Delay Time E0-E15 20 ns


tPHL Propagation Delay Time E0-E15 14 ns


Recommended Operating ConditionsSymbol Parameter DM54151A DM74151A Units

Min Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.8 0.8 V

IOH High Level Output Current −0.8 −0.8 mA

IOL Low Level Output Current 16 16 mA

TA Free Air Operating Temperature −55 125 0 70 ˚C

’151A Electrical Characteristicsover recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 5)

VI Input Clamp Voltage VCC = Min, II = −12 mA −1.5 V

VOH High Level Output VCC = Min, IOH = Max 2.4 V

Voltage VIL = Max, VIH = Min

VOL Low Level Output VCC = Min, IOL = Max 0.4 V

Voltage VIH = Min, VIL = Max

II Input Current @ Max VCC = Max, VI = 5.5V 1 mA

Input Voltage

IIH High Level Input Current VCC = Max, VI = 2.4V 40 µA

IIL Low Level Input Current VCC = Max, VI = 0.4V −1.6 mA

IOS Short Circuit VCC = Max DM54 −20 −55 mA

Output Current (Note 6) DM74 −18 −55

ICC Supply Current VCC = Max, (Note 7) 27 48 mA

Note 5: All typicals are at VCC = 5V, TA = 25˚C.

Note 6: Not more than one output should be shorted at a time.

Note 7: ICC is measured with the strobe and data select inputs at 4.5V, all other inputs and outputs open.

3 www.fairchildsemi.com

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’151A Switching Characteristicsat VCC = 5V and TA = 25˚C

Symbol Parameter From (Input) RL = 400Ω, CL = 15 pF Units

To (Output) Min Max


Low to High Level Output (4 Levels) to Y


High to Low Level Output (4 Levels) to Y


Low to High Level Output (3 Levels) to W


High to Low Level Output (3 Levels) to W


Low to High Level Output to Y


High to Low Level Output to Y





tPLH Propagation Delay Time D0-D7 24 ns

Low to High Level Output to Y

tPHL Propagation Delay Time D0-D7 24 ns

High to Low Level Output to Y

tPLH Propagation Delay Time D0-D7 14 ns


tPHL Propagation Delay Time D0-D7 14 ns



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Logic Diagrams

150

DS006546-3


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Logic Diagrams

151A

DS006546-4

See Address Buffers Below

Address Buffers for54151A/74151A

DS006546-5


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Function Tables

54150/74150Inputs Outputs

Select Strobe W

D C B A S

X X X X H H

L L L L L E0

L L L H L E1

L L H L L E2

L L H H L E3

L H L L L E4

L H L H L E5

L H H L L E6

L H H H L E7

H L L L L E8

H L L H L E9

H L H L L E10

H L H H L E11

H H L L L E12

H H L H L E13

H H H L L E14

H H H H L E15

H = High Level, L = Low Level, X = Don’t CareE0 , E1 …E15 = the complement of the level of the respective E input

54151A/75151AInputs Outputs

Select Strobe Y W

C B A S

X X X H L H

L L L L D0 D0

L L H L D1 D1

L H L L D2 D2

L H H L D3 D3

H L L L D4 D4

H L H L D5 D5

H H L L D6 D6

H H H L D7 D7

H = High Level, L = Low Level, X = Don’t CareD0, D1…D7 = the level of the respective D input


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Capítulo 4.- Dispositivos Secuenciales

4.1.- Elemento de memoria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2

4.1.1.- Tipos de biestables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2

4.2.- Contadores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4

4.3.- Temporizador . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10

4.5.- Registros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10

4.5.1.- Tipos de registros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10

4.6.- Referencias del capítulo 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18

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Capítulo 4.- Dispositivos SecuencialesUn circuito secuencial es aquel en el que sus salidas son consecuencia de las

señales de entrada y/o de la historia anterior de éstas. Para que esto pueda serposible, el circuito tiene que “recordar” lo que ha sucedido anteriormente. Por esoempezamos repasando los elementos de memoria.

4.1.- Elemento de memoria

En Electrónica Digital, un elemento de memoria es un circuito que es capaz demantener información digital permanentemente a lo largo del tiempo. En ElectrónicaAnalógica, esto se logra utilizando condensadores ideales en los que depositamos unacarga eléctrica y allí se queda mientras no actuemos sobre ella para cambiarla. Pordesgracia el condensador ideal no existe (como corresponde a su nombre) por lo queeste tipo de memoria analógica tiene una duración muy limitada en el tiempo.

Sin embargo, utilizando técnicas de conmutación (técnicas digitales un nuestrocaso) sí es posible disponer de elementos capaces de mantener la información. Sonlos denominados biestables.

4.1.1.- Tipos de biestables

En los libros de teoría nos encontramos con muchos tipos de biestables. En laindustria electrónica el número diferentes de biestables se reduce mucho respecto ala teoría. Por último, nosotros utilizamos intensamente un solo tipo de biestablesaunque en este documento hablaremos de tres, el tipo RS, como el más básico y elbiestable tipo D y el tipo JK.

Biestable tipo RS: La figura 4.1a muestra la circuitería lógica de un biestable RSconstruido con puertas NOR. Las salidas del circuito se mantienen en los nivelescorrespondientes hasta que se modifica la combinación de las señales deentrada. En la figura se ha incluído la tabla de verdad que define elfuncionamiento de este biestable. La figura 4.1b muestra el esquema de unbiestable RS NAND y su tabla de verdad.

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Figura 4.1b. Esquema de un biestable RS NAND y su tabla de verdad.

Figura 4.1a. Esquema de un biestable RS NOR y su tabla de verdad.

Figura 4.2a. Tabla de verdad de un biestable D.

Biestable tipo D: Este es un biestable que no funciona como el anteriorcambiando dos señales de entrada sino que su funcionamiento se basa en elflanco de una señal de control que se denomina reloj (clock). En la tabla deverdad que define su funcionamiento y que se ha incluido en la figura 4.2a,podemos ver que mientras que la señal se reloj se mantiene a nivel alto (H), anivel bajo (L) o si hay un cambio de alto a bajo (ú), la salida del biestable nocambia respecto a su estado anterior (Qn = Qn-1). Solamente cuando existe unflanco ascendente en la señal CK (ü) la salida toma el mismo estado que laentrada D. En esta situación se dice que en Q se copia el estado de la entrada D.

Es decir, que con el flanco ascendente de la señal CK el estado de laentrada D se almacena en este dispositivo hasta el próximo flanco ascendente elCK. Por lo tanto, el biestable es una memoria digital de un bit.

La figura 4.2b muestra el esquema digital de un biestable D con entrada deactivación (preset, /PRE) y borrado (clear, /CLR).

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Figura 4.2b. Esquema digital de un biestable D.

Figura 4.3. Esquema eléctrico (electrónico) de un biestable tipo D.

La figura 4.3 muestra el esquema eléctrico de un biestable D. Como puedeverse en esta figura, la complejidad del circuito es elevada, por lo que suele serhabitual no utilizar el circuito eléctrico (con transistores, resistencias, etc.) sino elesquema digital o su símbolo, como en la figura 4.2b.

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Figura 4.4. Símbolo del biestable JK y tabla de verdad.

No es frecuente almacenar un solo bit de información digital, es pocopráctico, por eso se construyen asociaciones de biestables que junto con circuitoscombinacionales forman los circuitos secuenciales y memorias.

La referencia 74LS74 es un dispositivo que contiene dos biestables D comolos descritos en los párrafos anteriores.

Biestable tipo JK: Un biestable tipo JK tiene un símbolo como el que se muestraen la figura 4.4 junto a su tabla de verdad.

La referencia 74LS76 es un dispositivo que contiene dos biestables tipo JKcomo los descritos en los párrafos anteriores.

4.2.- Contadores

Los contadores junto con los registros son los elementos más utilizados enelectrónica digital avanzada. Los contadores son estructuras que agrupan de formasdiferentes biestables y circuitos combinacionales para obtener una determinadafuncionalidad. No nos introducimos en su diseño, sino que describimos su circuiteríay su funcionamiento.

Contador binario en cascada de 4 bits: Se denomina así a la estructurarepresentada en la figura 4.5 a). En ella podemos ver 4 biestables D conectadosen serie. Esta es la estructura más simple para un contador binario y sucronograma de funcionamiento lo tenemos en la figura 4.5 b).

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Figura 4.5. Esquema digital de un contador binario.

En el cronograma (figura 4.5 b), podemos ver que las combinaciones de lassalidas Q3-Q0 van contando en binario desde 0000 hasta 1111, o lo que es lomismo, desde 0 hasta 15 en decimal.

Esta estructura de contador también se denomina “ripple” y asíncrono ya quecada biestable actúa después de hacerlo el anterior, no a la vez.

Ver la referencia 74HVC393.

Contador binario síncrono de 4 bits: Esta es una estructura diferente a laanterior en cuanto que todos los biestables evolucionan síncronamente con laseñal del reloj. El modelo comercial 74LS161 es un ejemplo de esta estructura yes el que se ha representado en la figura 4.6.

Los contadores no tiene porque contar siempre por un número que seapotencia de 2, Añadiendo algo de circuitería podemos contar por cualquiernúmero entero entre 0 y 2n, siendo n el nº de biestables en el contador. De hechoel modelo citado es programable en la cuenta desde 1 hasta 15. La figura xxmuestra el cronograma de funcionamiento de este contador. Este modelo decontador es además programable, es decir que se le puede utilizar para contarel número que queremos. Esto es lo que describe en el cronograma de la figura4.7. Dado que el contador cuenta de 0 a 15 (decimal) si se quiere que la cuentasea solamente por tres, le cargamos un valor 12 (1100 en binario). La salida RCOdel contador se pone a nivel alto durante un periodo de la señal de reloj cuandollega al final de la cuenta, indicando con ello esta situación. Hay que tenerpresente, como describe el cronograma, que el contador, una vez que llega a 15,pasa al valor cero y continúa contando ce nuevo hacia 15. Es decir que siqueremos que solo cuente tres en cada ocasión hay que volver a cargar el valor1100 a su entrada cada vez que termina la cuenta.

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Figura 4.6. Esquemadigital del contadorbinario 74LS161.

Contador hacia adelante (up): Los casos vistos anteriormente son contadoresadelante, la evolución de la cuenta va de 0 a 2n -1, siendo n el nº de biestablesutilizados para la cuenta.

Contador hacia atrás (down): Los contadores atrás realizan la cuanta desde elvalor superior hacia cero. En determinados casos esto es interesante y confrecuencia nos encontramos con contadores que permiten cuenta hacia adelantey hacia atrás. La figura 4.8 muestra el esquema digital del modelo 74LS191 quees un contador binario de 4 bits, up-down, programable y síncrono.

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Figura 4.7. Cronograma funcional del dispositivo 74LS161.

La señal de control D/U (figura 4.8) es la que permite seleccionar la formade conteo de este dispositivo: D/U = H ÿ cuenta hacia adelante (up); D/U = L ÿcuenta hacia atrás (down).

La figura 4.9 muestra el cronograma que define el funcionamiento de estecontador.

Como puede comprobarse en los últimos dispositivos que hemosdescrito, si no disponemos del cronograma, es muy difícil saber cómo funciona.De ahí la importancia de estos gráficos.

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Figura 4.8. Esquema digital del contador up-down 74LS191.

Dada la complejidad que tienen estos dispositivos, no es prácticorepresentarlos según la figura 4.8. Lo más utilizado es una representación muchomás simple como se muestra en la figura 4.10, en donde el dispositivo serepresenta por medio de un simple rectángulo al que se añade por el ladoizquierdo las señales de entrada y por el lado derecho las señales de salida y,muy importante, un texto indicando el modelo del dispositivo.

Además, en el símbolo se ha de indicar los nombres de todas las señalessegún las describe el fabricante y el número de la patilla a la que está conectadacada señal.

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Figura 4.9. Cronograma de funcionamiento del dispositivo 74LS191.

Figura 4.10. Símbolo

simplificadodel dispositivo

74LS191


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4.3.- Temporizador

Cuando la señal de entrada a un contador es una señal de periodo constante sussalidas nos está indicando intervalos de tiempo que son múltiplos del periodo de laseñal de entrada. Por eso, un temporizador no es más que un contador utilizado paracontar periodos de la señal. Si por ejemplo, la señal del reloj es de 1 MHz (periodo de1 :s), un contador de 32 bits (32 biestables) puede contar hasta 232 :s, es decir4.294.967.296 :s = 136,19 años.

4.4.- Divisor de frecuencia

De forma similar a lo descrito en el apartado anterior, si la señal de entrada a uncontador es periódica de periodo T ,cada una de las salidas de los biestables nos dauna señal periódica de periodo 2T, 4T, 8T, 16T, etc. Es decir, un divisor digital defrecuencia es un contador del cual utilizamos determinadas salidas cuando su entradaes periódica.

4.5.- Registros

Los registros son estructuras basadas en biestables como los contadores perodiferentes de éstos en su conexionado y en su funcionalidad.

4.5.1.- Tipos de registros

Dependiendo de como se conectan los biestables que forman un registro seobtienen distintas funciones. Estas funciones son las que definen los tipos de registrosque presentamos a continuación.

Entrada paralelo - salida paralelo : Son registros a los que se accede con n bitsen paralelo y se obtienen los mismos n bits en paralelo. Este tipo de registro seutiliza para almacenar información (típicamente 8 bits). El modelo comercial dereferencia es el 74LS374. La figura 4.11 representa el esquema digital de esteregistro. En esta figura podemos ver que hay dos modelos (74LS373 y 74LS374)que se diferencian en que el primero es un registro transparente y es segundofunciona por flanco de la señal reloj (CLK). La figura 4.12 muestra la tabla deverdad de ambos registros. Ambos modelos tienen salida triestado y tienen unaalta capacidad de corriente de salida (24 mA). En SBM se utiliza mucho el modelo74LS374. Ver la referencia 74LS374. Este tipo de registro es el que forma las

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Figura 4.11. Esquema digital de los registros 74LS373 y 74LS374.

Figura 4.12. Tablas funcionales de los registros dela figura 4.11.

células de una memoria RAM, como se verá en el capítulo dedicado a estosdispositivos.

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V1.0 4.13

Figura 4.13. Esquema básico de un registro de desplazamiento de 4bits y cronograma de funcionamiento.

Registros de desplazamiento : Se denominan así los registros que permitencambiar la posición relativa de los bits de un dato de más de un bit. Se trata deun conjunto de biestables conectados de serie y con la señal de reloj es comúna todos ellos. La imagen más clásica de ete tipo de conexión es la que se muestraen la figura 4.13. En ella podemos ver que

En ella podemos ver que si suponemos que partimos del estado “L” en todoslos biestables, la información binaria introducida por Di para por todos losbiestables del registro produciendo las correspondientes salidas en Q0 - Q3. Losdistintos instante del funcionamiento según el cronograma (a - h) quedandelimitados por los flancos de subida de la señal de reloj porque se han utilizadobiestables tipo D por flanco de subida.

Observando los contenidos de los biestables, podemos ver que cada uno deellos contiene la información de la entrada pero en distintos instantes de tiempomarcados por la señal CK. Este desplazamiento de la información binaria de unbiestable a otro es lo que da nombre a este tipo de registro.

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V1.0 4.14

Figura 4.14

Figura 4.15. Tabla de verdad del esquema de la figura 4.14.

Entrada serie - salida paralelo: Cuando utilizamos un registro dedesplazamiento para almacenar información, la entrada de la información binariapuede hacerse en serie como se muestra en la figura 4.13. Si disponemos de lasalida de cada uno de los biestables, se dice que la salida del registro es enparalelo (figura 4.13). El modelo comercial 74VHC164 es un ejemplo de este tipode registro de desplazamiento. La figura 4.14 muestra el esquema digital de estedispositivo. La figura 4.15 contiene la tabla de verdad que define elfuncionamiento de la figura 4.14.

Entrada serie - salida serie: Si en la figura 5.13 sólo disponemos de la salida deun biestable (el último de la derecha) el registro se dice que es de entrada enserie y salida en serie.

Entrada paralelo - salida paralelo: También es posible introducir la informaciónbinaria en paralelo en cada uno de los biestables. Si además las salidas de losbiestables están accesibles, entonces el registro de desplazamiento es de entradaen paralelo y salida en paralelo. Prestar atención para no confundir con el modelo74LS374 que es un registro de entrada en paralelo y salida en paralelo pero NOes un registro de desplazamiento y, por lo tanto su funcionamiento es totalmentediferente. La figura 4.16 muestra el esquema digital del modelo comercial74HC299 que es un registro de desplazamiento de entrada y salida en paralelo.En este caso y con el objeto de reducir el número de patillas del dispositivo, elfabricante ha utilizado las mismas patillas para la información de entrada y desalida. Por medio de las señales de control de salida /OE1 y /OE2 podemos hacerque las patillas I/O7 a I/O0 sean entradas o salidas del registro. Esto es bastante

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V1.0 4.15

Figura 4.16 Esquemadigital del registro dedesplazamiento74HC299.

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1 Prestar atención a que en la representación gráfica aparece un desplazamiento a laderecha debido al orden en el que se han representado de los biestables.

V1.0 4.16

razonable ya mientras escribimos la información binaria en el registro nonecesitamos disponer de las señales de salida ya que son iguales a las señalesde entrada. De esta forma el dispositivo necesita ocho patillas menos que si lasentradas y salidas son totalmente independientes.

Entrada paralelo - salida serie: Si en el dispositivos de la figura 5.13 utilizamosuna sola patilla de salida, decimos que tenemos la salida del registro en serie. Elmodelo comercial 74LS165 (ver referencia) es un registro de desplazamiento deocho bits con entrada en paralelo y salida exclusivamente en serie (por el últimobiestable).

Recirculación: Este es un caso para los registros de desplazamiento de entradaserie y salida serie en el que el dato de salida en serie se conecta al dato deentrada en serie. En esta situación, una vez cargado el dato, cada flanco de relojcambia la posición de los bits pero no desaparece la información del registro. Asísi el registro de es 8 bits, lada 8 flancos de reloj tenemos la misma informaciónen el mismo orden en el que se introdujo. Es decir que la información recirculauna y otra vez hasta que decidamos cambiarla.

Tipos de desplazamientos: Hasta ahora se ha visto el desplazamiento que sedenomina a la izquierda en el que cada desplazamiento hace que cada bit de lainformación existente en el registro pase a una posición de mayor peso numérico(bit0 pasa a bit1, bit1 pasa a bit2, etc.)1. Sin embargo en muchas ocasionesnecesitamos realizar desplazamiento a la derecha. Esto se consigue cambiandoel orden de las conexiones de los biestable.

Tipos de rotaciones: Similar a lo dicho para los tipos de desplazamiento.

Otras opciones: Cabe pensar en dispositivos que permitan rotaciones ydesplazamientos a derecha e izquierda seleccionable por medio de señales decontrol. Esto es lo que encontramos en la ULA de los :P.

Propiedades de los desplazamientos: Entre las propiedades de losdesplazamientos lógicos tenemos dos muy importantes:

• Multiplicación y división por 2. Un desplazamiento a izquierda de unainformación numérica significa matemáticamente una multiplicación del

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2 Hay que tener presente que si el número es impar la división tendrá un resto y estaoperación de desplazamiento no lo tiene en cuenta.

V1.0 4.17

valor numérico por la base. En el caso de un número binario es unamultiplicación por 2. Así, si al número binario 01000100 (68) le aplicamosun desplazamiento a la izquierda pasa a ser 10001000 (136) de valordoble al primero. Por otro lado, un desplazamiento a la derecha significauna división por la base del valor numérico, 2 en el caso binario2. Elnúmero binario 01010110 (86) para a ser 00101011 (43) al aplicarle undesplazamiento a la derecha. De forma similar, dos desplazamientosequivale a multiplicar o dividir por 4, etc.

• Generación de señales con forma específica. Tanto los desplazamientocon rotación como sin ella, las salidas de los registros de desplazamientonos permiten construir forma de onda digitales específicas combinandola información del registro, la recirculación o no y los flancos de reloj.

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V1.0 4.18

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V1.0 4.19


ectró

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SDLS119 − DECEMBER 1983 − REVISED MARCH 1988


Copyright 1988, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&*%$"# $ " #'&$$!"# '& "+& "&# &,!# #"%&"##"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*&"&#"/ !)) '!!&"&#

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5-1

FAST AND LS TTL DATA

DUAL JK FLIP-FLOPWITH SET AND CLEAR

The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-rect Clear inputs. These dual flip-flops are designed so that when the clockgoes HIGH, the inputs are enabled and data will be accepted. The Logic Levelof the J and K inputs will perform according to the Truth Table as long as mini-mum set-up times are observed. Input data is transferred to the outputs on theHIGH-to-LOW clock transitions.

MODE SELECT — TRUTH TABLE

OPERATING MODEINPUTS OUTPUTS

OPERATING MODESD CD J K Q Q

SetReset (Clear)*UndeterminedToggleLoad “0” (Reset)Load “1” (Set)Hold

LHLHHHH

HLLHHHH

XXXhlhl

XXXhhll

HLHqLHq

LHHqHLq

*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictableif SD and CD go HIGH simultaneously.

H,h = HIGH Voltage LevelL,l = LOW Voltage LevelX = Immateriall, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time priorto the HIGH-to-LOW clock transition

LOGIC DIAGRAM

Q

CLEAR (CD)

J

CLOCK (CP)

K

SET (SD)

Q

SN54/74LS76A

DUAL JK FLIP-FLOPWITH SET AND CLEAR

LOW POWER SCHOTTKY

LOGIC SYMBOL

16

1

4

15

14

K Q

CP

J Q

SD

VCC = PIN 5GND = PIN 13

12

6

9

11

10

K Q

CP

J QCD

7

J SUFFIXCERAMIC

CASE 620-09

N SUFFIXPLASTIC

CASE 648-08

161

16

1


SN54LSXXJ CeramicSN74LSXXN PlasticSN74LSXXD SOIC

161

D SUFFIXSOIC

CASE 751B-03

2

3 8

CD

SD

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5-2

FAST AND LS TTL DATA

SN54/74LS76A

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage 5474

4.54.75

5.05.0

5.55.25

V

TA Operating Ambient Temperature Range 5474

–550

2525

12570

°C

IOH Output Current — High 54, 74 –0.4 mA

IOL Output Current — Low 5474

4.08.0

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

S b l P

Limits

U i T C di iSymbol Parameter Min Typ Max Unit Test Conditions

VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs

VIL Input LOW Voltage54 0.7

VGuaranteed Input LOW Voltage for

VIL Input LOW Voltage74 0.8

Vp g

All Inputs

VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

VOH Output HIGH Voltage54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIHVOH Output HIGH Voltage74 2.7 3.5 V

CC , OH , IN IHor VIL per Truth Table

VOL Output LOW Voltage54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VIN = VIL or VIHVOL Output LOW Voltage74 0.35 0.5 V IOL = 8.0 mA

VIN = VIL or VIHper Truth Table

IIH Input HIGH Current

J, KClearClock

206080

µA VCC = MAX, VIN = 2.7 V

IIH Input HIGH CurrentJ, KClearClock

0.10.30.4

mA VCC = MAX, VIN = 7.0 V

IIL Input LOW CurrentJ, KClear, Clock

–0.4–0.8 mA VCC = MAX, VIN = 0.4 V

IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

ICC Power Supply Current 6.0 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

S b l P

Limits


fMAX Maximum Clock Frequency 30 45 MHzV 5 0 V

tPLH Clock Clear Set to Output15 20 ns

VCC = 5.0 VCL = 15 pFPLH

tPHLClock, Clear, Set to Output

15 20 nsCL = 15 pF

AC SETUP REQUIREMENTS (TA = 25°C)

S b l P

Limits


tW Clock Pulse Width High 20 ns

V 5 0 VtW Clear Set Pulse Width 25 ns

VCC = 5 0 Vts Setup Time 20 ns

VCC = 5.0 V

th Hold Time 0 ns

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74V

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Du

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-Bit B

inary

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©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com74VHC393 Rev. 1.5.0

December 2007

74VHC393

Dual 4-Bit Binary Counter

Features

High Speed: fMAX

= 170MHz (Typ.) at TA

= 25°C

Low power dissipation: ICC

= 4µA (Max.) at TA

= 25°C

High noise immunity: VNIH

= VNIL

= 28% VCC (Min.)

Power down protection is provided on all inputs

Pin and function compatible with 74HC393

General Description

The VHC393 is an advanced high speed CMOS 4-bit

Binary Counter fabricated with silicon gate CMOS tech-

nology. It achieves the high speed operation similar to

equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation. It contains two indepen-

dent counter circuits in one package, so that counting or

frequency division of 8 binary bits can be achieved with

one IC. This device changes state on the negative going

transition of the CLOCK pulse. The counter can be reset

to “0” (Q0–Q3

= “L”) by a HIGH at the CLEAR input

regardless of other inputs.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery back

up. This circuit prevents device destruction due to mis-

matched supply and input voltages.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74VHC393M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

74VHC393SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC393MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm WideElec

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©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com74VHC393 Rev. 1.5.0 2

74V

HC

393 —

Du

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-Bit B

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Connection Diagram

Pin Descriptions

Logic Symbol/s

IEEE/IEC

Truth Table

X: Don’t Care

System Diagram

Pin Names Description

CLR1, CLR2 Clear Inputs

CP1, CP2 Clock Pulse Inputs

QA, QB, QC, QD Outputs

Inputs Outputs

CP CLR QA QB QC QD

X H L L L L

L Count Up

L No Change

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74V

HC

393 —

Du

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-Bit B

inary

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Timing ChartEl

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74V

HC

393 —

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-Bit B

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Absolute Maximum RatingsStresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Recommended Operating Conditions(1)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Note:

1. Unused inputs must be held HIGH or LOW. They may not float.

Symbol Parameter Rating

VCC Supply Voltage –0.5V to +7.0V

VIN DC Input Voltage –0.5V to +7.0V

VOUT DC Output Voltage –0.5V to VCC + 0.5V

IIK Input Diode Current –20mA

IOK Output Diode Current(4) ±20mA

IOUT DC Output Current ±25mA

ICC DC VCC / GND Current ±75mA

TSTG Storage Temperature –65°C to +150°C

TL Lead Temperature (Soldering, 10 seconds) 260°C


VCC Supply Voltage 2.0V to +5.5V

VIN Input Voltage 0V to +5.5V

VOUT Output Voltage 0V to VCC

TOPR Operating Temperature –40°C to +85°C

tr, tf Input Rise and Fall Time

VCC

= 3.3V ±0.3V

VCC

= 5.0V ±0.5V

0

∼ 100ns/V

0

∼ 20ns/V

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DC Electrical Characteristics

Symbol Parameter VCC (V) Conditions

TA

= 25°C

TA

= –40°C to

+85°C

UnitsMin. Typ. Max. Min. Max.

VIH HIGH Level Input

Voltage

2.0 1.50 1.50 V

3.0 – 5.5 0.7 x VCC 0.7 x VCC

VIL LOW Level Input

Voltage

2.0 0.50 0.50 V

3.0 – 5.5 0.3 x VCC 0.3 x VCC

VOH HIGH Level Output

Voltage

2.0 VIN

= V IH

or VIL

IOH

= –50µA 1.9 2.0 1.9 V

3.0 2.9 3.0 2.9

4.5 4.4 4.5 4.4

3.0 IOH

= –4mA 2.58 2.48 V

4.5 IOH

= –8mA 3.94 3.80

VOL LOW Level Output

Voltage

2.0 VIN

= V IH

or VIL

IOL

= 50µA 0.0 0.1 0.1 V

3.0 0.0 0.1 0.1

4.5 0.0 0.1 0.1

3.0 IOL

= 4mA 0.36 0.44 V

4.5 IOL

= 8mA 0.36 0.44

IIN Input Leakage

Current

0 – 5.5 VIN

= 5.5V or GND ±0.1 ±1.0 µA

ICC Quiescent Supply

Current

5.5 VIN

= VCC or GND 4.0 40.0 µA

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-Bit B

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AC Electrical Characteristics

Note:

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating

current consumption without load Average operating current can be obtained by the equation:

ICC(Opr.)

= CPD • VCC • fIN + ICC / 2 (per Counter)

AC Operating Requirements


TA

= 25°C

TA

= –40°C to

+85°C


tPLH, tPHL Propagation Delay

Time (CP–QA)

3.3 ± 0.3 CL

= 15pF 8.6 13.2 1.0 15.5 ns

CL

= 50pF 11.1 16.7 1.0 19.0

5.0 ± 0.5 CL

= 15pF 5.8 8.5 1.0 10.0

CL

= 50pF 7.3 10.5 1.0 12.0


Time (CP–QB)

3.3 ± 0.3 CL = 15pF 10.2 15.8 1.0 18.5 ns

CL = 50pF 12.7 19.3 1.0 22.0

5.0 ± 0.5 CL = 15pF 6.8 9.8 1.0 11.5

CL = 50pF 8.3 11.8 1.0 13.5


Time (CP–QC)

3.3 ± 0.3 CL = 15pF 11.7 18.0 1.0 21.0 ns

CL = 50pF 14.2 21.5 1.0 24.5

5.0 ± 0.5 CL = 15pF 7.7 11.2 1.0 13.0

CL = 50pF 9.2 13.2 1.0 15.0


Time (CP–QD)

3.3 ± 0.3 CL = 15pF 13.0 19.7 1.0 23.0 ns

CL = 50pF 15.5 23.2 1.0 26.5

5.0 ± 0.5 CL = 15pF 8.5 12.5 1.0 14.5

CL = 50pF 10.0 14.5 1.0 16.5


Time (CLR–Qn)

3.3 ± 0.3 CL = 15pF 7.9 12.3 1.0 14.5 ns

CL = 50pF 10.4 15.8 1.0 18.0

5.0 ± 0.5 CL = 15pF 5.4 8.1 1.0 9.5

CL = 50pF 6.9 10.1 1.0 11.5

fMAX Maximum Clock 3.3 ± 0.3 CL = 15pF 75 120 65 MHz

CL = 50pF 45 65 35

5.0 ± 0.5 CL = 15pF 125 170 105

CL = 50pF 85 115 75

CIN Input Capacitance VCC = Open 4 10 10 pF

CPD Power Dissipation

Capacitance

(2) 23 pF

Symbol Parameter VCC (V)

TA = 25°C T A = – 40°C to +85°C

UnitsTyp. Guaranteed Minimum

tW(L), tW(H) Minimum Pulse Width (CP) 3.3 ± 0.3 5.0 5.0 ns

5.0 ± 0.5 5.0 5.0

tW(H) Minimum Pulse Width (CLR) 3.3 ± 0.3 5.0 5.0 ns

5.0 ± 0.5 5.0 5.0

tREM Minimum Removal Time 3.3 ± 0.3 5.0 5.0 ns

5.0 ± 0.5 4.0 4.0

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SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A, SN54S162,SN54S163, SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A,SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988



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SN54LS160A THRU SN54LS163A, SN54S162,SN54S163, SN74LS160A THRU SN74LS163A,SN74S162, SN74S163 SYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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SN54160, SN54162, SN74160, SN74162SYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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SN54161, SN54163, SN74161, SN74163SYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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SN54LS160A, SN54LS162A, SN74LS160A, SN74LS162ASYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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SN54LS161A, SN54LS163A, SN74LS161A, SN74LS163ASYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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SN54S162, SN74S162SYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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Aplic

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SN54S163, SN74S163SYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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Aplic

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SN54160, SN54162, SN54LS160A, SN54LS162A, SN54S162,SN74160, SN74162, SN74LS160A, SN74LS162A, SN74S162SYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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SN54161, SN54163, SN54LS161A, SN54LS163A, SN54S163,SN74161, SN74163, SN74LS161A, SN74LS163A, SN74S163SYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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SN54160 THRU SN54163, SN74160 THRU SN74163SYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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SN54LS160 THRU SN54LS163A, SN74LS160 THRU SN74LS163ASYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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SN54S162, SN54S163, SN74S162, SN74S163SYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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Elec

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SN54160 THRU SN54163, SN54LS160A THRU SN54LS163A,SN74160 THRU SN74163, SN74LS160A THRU SN74LS163A,SYNCHRONOUS 4-BIT COUNTERSSDLS060 – OCTOBER 1976 – REVISED MARCH 1988


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SN54190, SN54191, SN54LS190, SN54LS191,SN74190, SN74191, SN74LS190, SN74LS191SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROLSDLS072 – DECEMBER 1972 – REVISED MARCH 1988



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Elec

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SN54190, SN54LS190, SN74190, SN74LS190SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROLSDLS072 – DECEMBER 1972 – REVISED MARCH 1988


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Elec

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SN54190, SN54191, SN74190, SN74191SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROLSDLS072 – DECEMBER 1972 – REVISED MARCH 1988


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SN54LS190, SN54LS191, SN74LS190, SN74LS191SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROLSDLS072 – DECEMBER 1972 – REVISED MARCH 1988


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SN54LS373, SN54LS374, SN54S373, SN54S374,SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPSSDLS165B – OCTOBER 1975 – REVISED AUGUST 2002


Choice of Eight Latches or Eight D-TypeFlip-Flops in a Single Package

3-State Bus-Driving Outputs

Full Parallel Access for Loading

Buffered Control Inputs

Clock-Enable Input Has Hysteresis toImprove Noise Rejection (’S373 and ’S374)

P-N-P Inputs Reduce DC Loading on DataLines (’S373 and ’S374)

description

These 8-bit registers feature 3-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. Thehigh-impedance 3-state and increasedhigh-logic-level drive provide these registers withthe capability of being connected directly to anddriving the bus lines in a bus-organized systemwithout need for interface or pullup components.These devices are particularly attractive forimplementing buffer registers, I/O ports,bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 aretransparent D-type latches, meaning that whilethe enable (C or CLK) input is high, the Q outputsfollow the data (D) inputs. When C or CLK is takenlow, the output is latched at the level of the datathat was set up.

The eight flip-flops of the ’LS374 and ’S374 areedge-triggered D-type flip-flops. On the positivetransition of the clock, the Q outputs are set to thelogic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system designas ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A bufferedoutput-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logiclevels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus linessignificantly.

OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or newdata can be entered, even while the outputs are off.

Copyright 2002, Texas Instruments Incorporated


SN54LS373, SN54LS374, SN54S373,SN54S374 . . . J OR W PACKAGE

SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGESN74LS374 . . . DB, DW, N, OR NS PACKAGE

SN74S373 . . . DW OR N PACKAGE(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

8D7D7Q6Q6D

2D2Q3Q3D4D

SN54LS373, SN54LS374, SN54S373,SN54S374 . . . FK PACKAGE

(TOP VIEW)

1D 1Q OC

5Q 5D8Q

4QG

ND C

V CC

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OC1Q1D2D2Q3Q3D4D4Q

GND

VCC8Q8D7D7Q6Q6D5D5QC†

† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.

† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.

†

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.


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SN54LS373, SN54LS374, SN54S373, SN54S374,SN74LS373, SN74LS374, SN74S373, SN74S374OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPSSDLS165B – OCTOBER 1975 – REVISED AUGUST 2002




TOP-SIDEMARKING

Tube SN74LS373N SN74LS373N

PDIP NTube SN74LS374N SN74LS374N

PDIP – NTube SN74S373N SN74S373N

Tube SN74S374N SN74S374N




0°C to 70°C SOIC DWTape and reel SN74LS374DWR

LS374

0°C to 70°C SOIC – DWTube SN74S373DW

S373Tape and reel SN74S373DWR

S373

Tube SN74S374DWS374


Tape and reel SN74LS373NSR 74LS373

SOP – NS Tape and reel SN74LS374NSR 74LS374

Tape and reel SN74S374NSR 74S374

SSOP – DB Tape and reel SN74LS374DBR LS374A

Tube SN54LS373J SN54LS373J

Tube SNJ54LS373J SNJ54LS373J

Tube SN54LS374J SN54LS374J

CDIP JTube SNJ54LS374J SNJ54LS374J

CDIP – JTube SN54S373J SN54S373J

Tube SNJ54S373J SNJ54S373J

Tube SN54S374J SN54S374J

–55°C to 125°C Tube SNJ54S374J SNJ54S374J

Tube SNJ54LS373W SNJ54LS373W

CFP – W Tube SNJ54LS374W SNJ54LS374W

Tube SNJ54S374W SNJ54S374W

Tube SNJ54LS373FK SNJ54LS373FK

LCCC FKTube SNJ54LS374FK SNJ54LS374FK

LCCC – FKTube SNJ54S373FK SNJ54S373FK

Tube SNJ54S374FK SNJ54S374FK

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB designguidelines are available at www.ti.com/sc/package.El

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Function Tables

’LS373, ’S373(each latch)

INPUTS OUTPUTOC C D Q

L H H H

L H L L

L L X Q0

H X X Z

’LS374, ’S374(each latch)

INPUTS OUTPUTOC CLK D Q

L ↑ H H

L ↑ L L

L L X Q0

H X X Z

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logic diagrams (positive logic)

OC

for ’S373 Only

1

11

32

C

1D

C1

1D1Q

45

2D

C1

1D2Q

76

3D

C1

1D3Q

89

4D

C1

1D4Q

1312

5D

C1

1D5Q

1415

6D

C1

1D6Q

1716

7D

C1

1D7Q

1819

8D

C1

1D8Q

Pin numbers shown are for DB, DW, J, N, NS, and W packages.

OC

for ’S374 Only

1

11

32

CLK

1D

C1

1D1Q

45

2D 1D2Q

76

3D 1D3Q

89

4D 1D4Q

1312

5D 1D5Q

1415

6D 1D6Q

1716

7D 1D7Q

1819

8D 1D8Q

’LS373, ’S373Transparent Latches

’LS374, ’S374Positive-Edge-Triggered Flip-Flops

C1

C1

C1

C1

C1

C1

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schematic of inputs and outputs

Output


VCC

100 Ω NOM

VCC

Req = 20 kΩ NOM

Input

Input

VCC

17 kΩ NOM

’LS373

EQUIVALENT OF DATA INPUTS EQUIVALENT OF ENABLE- ANDOUTPUT-CONTROL INPUTS

EQUIVALENT OF CLOCK- ANDOUTPUT-CONTROL INPUTS

’LS374

EQUIVALENT OF DATA INPUTS

30 kΩ NOM

Input

VCC

17 kΩ NOM

VCC

Input

Output


VCC

100 Ω NOM

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †(’LS devices)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-state output voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .





SN54LS’ SN74LS’UNIT


VCC Supply voltage 4.5 5 5 4.75 5 5.25 V

VOH High-level output voltage 5.5 5.5 V

IOH High-level output current –1 –2.6 mA


t Pulse durationCLK high 15 15

nstw Pulse durationCLK low 15 15

ns

t Data setup time’LS373 5↓ 5↓

nstsu Data setup time’LS374 20↑ 20↑

ns

th Data hold time’LS373 20↓ 20↓

nsth Data hold time’LS374‡ 5↑ 0↑

ns

TA Operating free-air temperature –55 125 0 70 °C‡ The th specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns (commercial only).

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PARAMETER TEST CONDITIONS†SN54LS’ SN74LS’


UNIT



VIK Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V

VOH High level output voltageVCC = MIN, VIH = 2 V,

2 4 3 4 2 4 3 1 VVOH High-level output voltage CC ,VIL = VIL max,

IH ,IOH = MAX

2.4 3.4 2.4 3.1 V

VOL Low level output voltageVCC = MIN, VIH = 2 V, IOL = 12 mA 0.25 0.4 0.25 0.4

VVOL Low-level output voltage CC ,VIL = VIL max

IH ,

IOL = 24 mA 0.35 0.5V

IOZHOff-state output current, VCC = MAX, VIH = 2 V,

20 20 AIOZH,

high-level voltage appliedCC ,

VO = 2.7 VIH ,

20 20 A

IOZLOff-state output current, VCC = MAX, VIH = 2 V,

20 20 AIOZL,

low-level voltage appliedCC ,

VO = 0.4 VIH ,

–20 –20 A

IIInput current at maximum

VCC = MAX VI = 7 V 0 1 0 1 mAII input voltageVCC = MAX, VI = 7 V 0.1 0.1 mA

IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 A

IIL Low-level input current VCC = MAX, VI = 0.4 V –0.4 –0.4 mA

IOS Short-circuit output current§ VCC = MAX –30 –130 –30 –130 mA

ICC Supply currentVCC = MAX, ’LS373 24 40 24 40

mAICC Supply current CC ,Output control at 4.5 V ’LS374 27 40 27 40

mA

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.


PARAMETERFROM TO

TEST CONDITIONS’LS373 ’LS374

UNITPARAMETER(INPUT) (OUTPUT)

TEST CONDITIONSMIN TYP MAX MIN TYP MAX

UNIT

fmaxRL = 667 Ω CL = 45 pF,

See Note 335 50 MHz

tPLHData Any Q

RL = 667 Ω CL = 45 pF, 12 18ns

tPHLData Any Q L L ,

See Note 3 12 18ns

tPLHC or CLK Any Q

RL = 667 Ω CL = 45 pF, 20 30 15 28ns

tPHLC or CLK Any Q L L ,

See Note 3 18 30 19 28ns

tPZHOC Any Q

RL = 667 Ω CL = 45 pF, 15 28 20 26ns

tPZLOC Any Q L L ,

See Note 3 25 36 21 28ns

tPHZ 15 25 15 28tPHZOC Any Q RL 667 Ω CL 5 pF

15 25 15 28ns

tPLZOC Any Q RL = 667 Ω CL = 5 pF

12 20 12 20ns

tPLZ 12 20 12 20

NOTE 3: Maximum clock frequency is tested with all outputs loaded.fmax = maximum clock frequencytPLH = propagation delay time, low-to-high-level outputtPHL = propagation delay time, high-to-low-level outputtPZH = output enable time to high leveltPZL = output enable time to low leveltPHZ = output disable time from high leveltPLZ = output disable time from low level

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schematic of inputs and outputs

EQUIVALENT OF EACH INPUT

VCC

Input

2.8 kΩ NOM

Output


VCC

50 Ω NOM

’S373 and ’S374 ’S373 and ’S374

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †(’S devices)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-state output voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .





SN54S’ SN74S’UNIT



VOH High-level output voltage 5.5 5.5 V

IOH High-level output current –2 –6.5 mA

t Pulse duration clock/enableHigh 6 6

nstw Pulse duration, clock/enableLow 7.3 7.3

ns

t Data setup time’S373 0↓ 0↓

nstsu Data setup time’S374 5↑ 5↑

ns

th Data hold time’S373 10↓ 10↓

nsth Data hold time’S374 2↑ 2↑

ns

TA Operating free-air temperature –55 125 0 70 °C

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electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted) (SN54S373, SN54S374, SN74S373, SN74S374)

PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT

VIH 2 V

VIL 0.8 V

VIK VCC = MIN, II = –18 mA –1.2 V

VOHSN54S’

VCC = MIN VIH = 2 V VIL = 0 8 V IOH = MAX2.4 3.4

VVOH SN74S’VCC = MIN, VIH = 2 V, VIL = 0.8 V, IOH = MAX

2.4 3.1V

VOL VCC = MIN, VIH = 2 V, VIL = 0.8 V, IOL = 20 mA 0.5 V

IOZH VCC = MAX, VIH = 2 V, VO = 2.4 V 50 A

IOZL VCC = MAX, VIH = 2 V, VO = 0.5 V –50 A

II VCC = MAX, VI = 5.5 V 1 mA

IIH VCC = MAX, VI = 2.7 V 50 A

IIL VCC = MAX, VI = 0.5 V –250 A

IOS§ VCC = MAX –40 –100 mA

Outputs high 160

’S373 Outputs low 160

Outputs disabled 190

ICC VCC = MAX Outputs high 110 mA

’S374Outputs low 140

’S374Outputs disabled 160

CLK and OC at 4 V, D inputs at 0 V 180

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC= 5 V, TA = 25°C.§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.


PARAMETERFROM TO

TEST CONDITIONS’S373 ’S374

UNITPARAMETER(INPUT) (OUTPUT)

TEST CONDITIONSMIN TYP MAX MIN TYP MAX

UNIT

fmaxRL = 280 Ω CL = 15 pF,

See Note 375 100 MHz

tPLHData Any Q

RL = 280 Ω CL = 15 pF, 7 12ns

tPHLData Any Q L L ,

See Note 3 7 12ns

tPLHC or CLK Any Q

RL = 280 Ω CL = 15 pF, 7 14 8 15ns

tPHLC or CLK Any Q L L ,

See Note 3 12 18 11 17ns

tPZHOC Any Q

RL = 280 Ω CL = 15 pF, 8 15 8 15ns

tPZLOC Any Q L L ,

See Note 3 11 18 11 18ns

tPHZOC Any Q RL = 280 Ω CL = 5 pF

6 9 5 9ns

tPLZOC Any Q RL = 280 Ω CL = 5 pF

8 12 7 12ns

NOTE 3. Maximum clock frequency is tested with all outputs loaded.fmax = maximum clock frequencytPLH = propagation delay time, low-to-high-level outputtPHL = propagation delay time, high-to-low-level outputtPZH = output enable time to high leveltPZL = output enable time to low leveltPHZ = output disable time from high leveltPLZ = output disable time from low level

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tPHL tPLH

tPLH tPHL


High-LevelPulse

Low-LevelPulse


Input

Out-of-PhaseOutput

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-PhaseOutput

(see Note D)


VCC

RL

Test Point


CL(see Note A)



(see Note B)

VCC

RLFrom Output

Under Test

CL(see Note A)

TestPoint

(see Note B)

VCCRL


CL(see Note A)

TestPoint

5 kΩ


Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.G. The outputs are measured one at a time with one input transition per measurement.H. All parameters and waveforms are not applicable to all devices .

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu


TimingInput

DataInput

3 V

0 V

OutputControl

(low-levelenabling)


and D)


and D) ≈1.5 V

VOH – 0.5 V

VOL + 0.5 V

≈1.5 V


1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V

1.3 V

tw

1.3 V 1.3 V

1.3 V 1.3 V

1.3 V 1.3 V

VOL

VOH


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PARAMETER MEASUREMENT INFORMATIONSERIES 54S/74S DEVICES

tPHL tPLH

tPLH tPHL


High-LevelPulse

Low-LevelPulse


Input

Out-of-PhaseOutput

(see Note D)

3 V

0 V

VOL

VOH

VOH

VOL

In-PhaseOutput

(see Note D)


VCC

RL

Test Point


CL(see Note A)



(see Note B)

VCC

RLFrom Output

Under Test

CL(see Note A)

TestPoint

(see Note B)

VCCRL


CL(see Note A)

TestPoint

1 kΩ


Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series

54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.F. The outputs are measured one at a time with one input transition per measurement.G. All parameters and waveforms are not applicable to all devices .

S1

S2

tPHZ

tPLZtPZL

tPZH

3 V

3 V

0 V

0 V

thtsu


TimingInput

DataInput

3 V

0 V

OutputControl

(low-levelenabling)


and D)


and D)≈1.5 V

VOH – 0.5 V

VOL + 0.5 V

≈1.5 V


1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

tw

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

VOH

VOL


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TYPICAL APPLICATION DATA

BidirectionalData Bus 2

OutputControl 2

Clock 2Clock 1

BidirectionalData Bus 1

OutputControl 1

Clock 1

Clock 2

H

BusExchange

ClockH

Clock Circuit for Bus Exchange

AB

Expandable 4-Word by 8-Bit General Register File

Enable Select

1/2 SN74LS139or SN74S139

’LS374 or ’S374

’LS374 or ’S374

’LS374 or ’S374

’LS374 or ’S374

1/2 SN74LS139or SN74S139

Y0Y1Y2Y3

Y0 Y1 Y2 Y3

A B G

ClockSelect Clock

’LS374or

’S374

’LS374or

’S374

G

1D2D3D4D5D6D7D8D

1Q2Q3Q4Q5Q6Q7Q8Q

1D2D3D4D5D6D7D8D

1Q2Q3Q4Q5Q6Q7Q8Q

C

C

Bidirectional Bus Driver

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74V

HC

164 —

8-B

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©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com74VHC164 Rev. 1.4.0

February 2008

74VHC164

8-Bit Serial-In, Parallel-Out Shift Register

Features

High Speed: fMAX

= 175MHz at VCC

= 5V

Low power dissipation: ICC

= 4µA (max.) at TA

= 25°C

High noise immunity: VNIH

= VNIL

= 28% VCC (min.)

Power down protection provided on all inputs

Low noise: VOLP

= 0.8V (max.)

Pin and function compatible with 74HC164

General Description

The VHC164 is an advanced high-speed CMOS device

fabricated with silicon gate CMOS technology. It

achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The VHC164 is a high-speed 8-Bit

Serial-In/Parallel-Out Shift Register. Serial data is

entered through a 2-input AND gate synchronous with

the LOW-to-HIGH transition of the clock. The device fea-

tures an asynchronous Master Reset which clears the

register, setting all outputs LOW independent of the

clock. An input protection circuit insures that 0V to 7V

can be applied to the input pins without regard to the

supply voltage. This device can be used to interface 5V

to 3V systems and two supply systems such as battery

backup. This circuit prevents device destruction due to

mismatched supply and input voltages.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order Number

Package

Number Package Description

74VHC164M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

74VHC164SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC164MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74VHC164N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WideElec

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74V

HC

164 —

8-B

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Connection Diagram

Pin Description

Functional Description

The VHC164 is an edge-triggered 8-bit shift register with

serial data entry and an output from each of the eight

stages. Data is entered serially through one of two inputs

(A or B); either of these inputs can be used as an active

High Enable for data entry through the other input. An

unused input must be tied HIGH.

Each LOW-to-HIGH transition on the Clock (CP) input

shifts data one place to the right and enters into Q0 the

logical AND of the two data inputs (A • B) that existed

before the rising clock edge. A LOW level on the Master

Reset (MR) input overrides all other inputs and clears

the register asynchronously, forcing all Q outputs LOW.

Logic Symbol

Function Table

H

= HIGH Voltage Levels

L

= LOW Voltage Levels

X

= Immaterial

Q

= Lower case letters indicate the state of the

referenced input or output one setup time prior to

the LOW-to-HIGH clock transition.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to

estimate propagation delays.

Pin

Names

Description

A, B Data Inputs

CP Clock Pulse Input (Active Rising Edge)

MR Master Reset Input (Active LOW)

Q0–Q7 Outputs

Operating

Mode

Inputs Outputs

MR A B Q0 Q1–Q7

Reset (Clear) L X X L L–L

Shift H L L L Q0–Q6

H L H L Q0–Q6

H H L L Q0–Q6

H H H H Q0–Q6

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Absolute Maximum RatingsStresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Recommended Operating Conditions(1)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Note:

1. Unused inputs must be held HIGH or LOW. They may not float.


VCC Supply Voltage –0.5V to +7.0V

VIN DC Input Voltage –0.5V to +7.0V

VOUT DC Output Voltage –0.5V to VCC + 0.5V

IIK Input Diode Current –20mA

IOK Output Diode Current ±20mA

IOUT DC Output Current ±25mA

ICC DC VCC / GND Current ±75mA

TSTG Storage Temperature –65°C to +150°C

TL Lead Temperature (Soldering, 10 seconds) 260°C


VCC Supply Voltage 2.0V to 5.5V

VIN Input Voltage 0V to +5.5V

VOUT Output Voltage 0V to VCC

TOPR Operating Temperature –40°C to +85°C

tr, tf Input Rise and Fall Time,

VCC

= 3.3V ± 0.3V

VCC

= 5.0V ± 0.5V

0ns/V

∼ 100ns/V

0ns/V

∼ 20ns/V

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DC Electrical Characteristics

Noise Characteristics

Note:

2. Parameter guaranteed by design.


TA

= 25°C

TA

= –40°C to

+85°C


VIH HIGH Level Input

Voltage

2.0 1.50 1.50 V

3.0–5.5 0.7 x VCC 0.7 x VCC

VIL LOW Level Input

Voltage

2.0 0.50 0.50 V

3.0–5.5 0.3 x VCC 0.3 x VCC

VOH HIGH Level

Output Voltage

2.0 VIN

= VIH

or VIL

IOH

= –50µA 1.9 2.0 1.9 V

3.0 2.9 3.0 2.9

4.5 4.4 4.5 4.4

3.0 IOH

= –4mA 2.58 2.48

4.5 IOH

= –8mA 3.94 3.80

VOL LOW Level

Output Voltage

2.0 VIN

= VIH

or VIL

IOL

= 50µA 0.0 0.1 0.1 V

3.0 0.0 0.1 0.1

4.5 0.0 0.1 0.1

3.0 IOL

= 4mA 0.36 0.44

4.5 IOL

= 8mA 0.36 0.44

IIN Input Leakage

Current

0–5.5 VIN

= 5.5V or GND ±0.1 ±1.0 µA

ICC Quiescent

Supply Current

5.5 VIN

= VCC or GND 4.0 40.0 µA


TA

= 25°C

UnitsTyp. Limits

VOLP(2) Quiet Output Maximum

Dynamic VOL

5.0 CL

= 50pF 0.5 0.8 V

VOLV(2) Quiet Output Minimum

Dynamic VOL

5.0 CL = 50pF –0.5 –0.8 V

VIHD(2) Minimum HIGH Level

Dynamic Input Voltage

5.0 CL = 50pF 3.5 V

VILD(2) Maximum LOW Level

Dynamic Input Voltage

5.0 CL = 50pF 1.5 VElec

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AC Electrical Characteristics

Note:

3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating

current consumption without load. Average operating current can be obtained from the equation:

ICC (opr.) = CPD • VCC • fIN + ICC.

AC Operating Requirements

Note:

4. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V


TA = 25°C

TA = –40°C

to +85°C


fMAX Maximum Clock

Frequency

3.3 ± 0.3 CL = 15pF, RL = 1kΩ 80 125 65 MHz

CL = 50pF, RL = 1kΩ 50 75 45

5.0 ± 0.5 CL = 15pF, RL = 1kΩ 125 175 105

CL = 50pF, RL = 1kΩ 85 115 75


Time (CP–Qn)

3.3 ± 0.3 CL = 15pF, RL = 1kΩ 8.4 12.8 1.0 15.0 ns

CL = 50pF, RL = 1kΩ 10.9 16.3 1.0 18.5

5.0 ± 0.5 CL = 15pF, RL = 1kΩ 5.8 9.0 1.0 10.5

CL = 50pF, RL = 1kΩ 7.3 11.0 1.0 12.5

tPHL Propagation Delay

Time (MR–Qn)

3.3 ± 0.3 CL = 15pF, RL = 1kΩ 8.3 12.8 1.0 15.0 ns

CL = 50pF, RL = 1kΩ 10.8 16.3 1.0 18.5

5.0 ± 0.5 CL = 15pF, RL = 1kΩ 5.2 8.6 1.0 10.0

CL = 50pF, RL = 1kΩ 6.7 10.6 1.0 12.0

CIN Input Capacitance VCC = Open 4 10 10 pF

CPD Power Dissipation

Capacitance

(3) 76 pF

Symbol Parameter

VCC (V)(4)

TA = 25°C

TA = –40°C

to +85°C

UnitsTyp.

Guaranteed

Minimum

tW(L), tW(H) Minimum Pulse Width (CP) 3.3 5.0 5.0 ns

5.0 5.0 5.0

tW(L) Minimum Pulse Width (MR) 3.3 5.0 5.0 ns

5.0 5.0 5.0

tS Minimum Setup Time 3.3 5.0 6.0 ns

5.0 4.5 4.5

tH Minimum Hold Time 3.3 0.0 0.0 ns

5.0 1.0 1.0

tREC Minimum Removal Time (MR) 3.3 2.5 2.5 ns

5.0 2.5 2.5

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1. General description

The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which arepin-compatible with Low-power Schottky TTL (LSTTL) devices. They are specified incompliance with JEDEC standard no. 7A.

The 74HC299; 74HCT299 contain eight edge-triggered D-type flip-flops and theinterstage logic necessary to perform synchronous shift-right, shift-left, parallel load andhold operations. An operation is determined by the mode select inputs S0 and S1, asshown in Table 3.

Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow them to operate as datainputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion inserial shifting of longer words.

A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CPinputs and resets the flip-flops. All other state changes are initiated by the rising edge ofthe clock pulse. Inputs can change when the clock is in either state, provided that therecommended set-up and hold times are observed.

A HIGH signal on the 3-state output enable inputs OE1 or OE2 disables the 3-statebuffers and the I/On outputs are set to the high-impedance OFF-state. In this condition,the shift, hold, load and reset operations still occur when preparing for a parallel loadoperation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1.

2. Features

n Multiplexed inputs/outputs provide improved bit density

n Four operating modes:

u Shift left

u Shift right

u Hold (store)

u Load data

n Operates with output enable or at high-impedance OFF-state (Z)

n 3-state outputs drive bus lines directly

n Cascadable for n-bit word lengths

n ESD protection:

u HBM JESD22-A114E exceeds 2000 V

u MM JESD22-A115-A exceeds 200 V

n Specified from −40 °C to +85 °C and from −40 °C to +125 °C

74HC299; 74HCT2998-bit universal shift register; 3-stateRev. 03 — 28 July 2008 Product data sheet

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74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 03 — 28 July 2008 2 of 24

NXP Semiconductors 74HC299; 74HCT2998-bit universal shift register; 3-state

3. Ordering information

4. Functional diagram

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC299

74HC299D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; bodywidth 7.5 mm

SOT163-1

74HC299DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads;body width 5.3 mm

SOT339-1

74HC299N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

74HC299PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;body width 4.4 mm

SOT360-1

74HCT299

74HCT299D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; bodywidth 7.5 mm

SOT163-1

74HCT299DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads;body width 5.3 mm

SOT339-1

74HCT299N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

74HCT299PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;body width 4.4 mm

SOT360-1

Fig 1. Functional diagram

001aai460

INPUT/3-STATE OUTPUT CIRCUITRY

8-BIT SHIFT REGISTER

I/O0

CP

Q0

MR

2

8

9

3

12

11 DSR

7

I/O1

13

I/O2

6

I/O3

14

I/O4

5 15

I/O5

1 19

I/O6

4

I/O7

16

Q7

S0 S1 DSL

17

18

OE1

OE2Elec

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Fig 2. Logic symbol Fig 3. IEC logic symbol

001aai458

MR

OE2

9

3

16

4

17

8

15

5

14

6

13

7

18

11

19

1

I/O7

I/O6

Q7

Q0

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

CP

S0

S1

DSR

DSL

12

923

R SRG8

3EN5

01

191

C4/1 /2

M03

12

118

1, 4D3, 4D

6, 5

18 2, 4D

7 Z6

17Z7

614

515

4

7, 5

001aai459

&

16

3, 4D

3, 4D

5

13

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Fig 4. Logic diagram

001aai461

DQ

CP

RDFF0

DQ

CP

RDFF1

DQ

CP

RDFF2

DQ

CP

RDFF3

DQ

CP

RDFF4

DQ

CP

RDFF5

DQ

CP

RDFF6

DQ

CP

RDFF7

DSR

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

S0

S1

CP

Q0

OE1

OE2

MR

DSL

Q7

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5. Pinning information

5.1 Pinning

5.2 Pin description

Fig 5. Pin configuration (SO20 and (T)SSOP20) Fig 6. Pin configuration (DIP20)

74HC29974HCT299

S0 VCC

OE1 S1

OE2 DSL

I/O6 Q7

I/O4 I/O7

I/O2 I/O5

I/O0 I/O3

Q0 I/O1

MR CP

GND DSR

001aai511

1

2

3

4

5

6

7

8

9

10

12

11

14

13

16

15

18

17

20

19

74HC29974HCT299

S0 VCC

OE1 S1

OE2 DSL

I/O6 Q7

I/O4 I/O7

I/O2 I/O5

I/O0 I/O3

Q0 I/O1

MR CP

GND DSR

001aai457

1

2

3

4

5

6

7

8

9

10

12

11

14

13

16

15

18

17

20

19

Table 2. Pin description

Symbol Pin Description

S0 1 mode select input

OE1 2 3-state output enable input (active LOW)

OE2 3 3-state output enable input (active LOW)

I/O6 4 parallel data input or 3-state parallel output (bus driver)




Q0 8 serial output (standard output)

MR 9 asynchronous master reset input (active LOW)

GND 10 ground (0 V)

DSR 11 serial data shift-right input

CP 12 clock input (LOW to HIGH, edge-triggered)





Q7 17 serial output (standard output)

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6. Functional description

[1] H = HIGH voltage level;

L = LOW voltage level;

↑ = LOW to HIGH CP transition;

X = don’t care.

7. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DSL 18 serial data shift-left input

S1 19 mode select input

VCC 20 positive supply voltage

Table 2. Pin description …continued

Symbol Pin Description

Table 3. Function table [1]

Input Response

MR S1 S0 CP

L X X X asynchronous reset; Q0 to Q7 = LOW

H H H ↑ parallel load; I/On → Qn

H L H ↑ shift right; DSR → Q0, Q0 → Q1, etc.

H H L ↑ shift left; DSL → Q7, Q7 → Q6, etc.

H L L X hold

Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +7 V

IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] - ±20 mA

IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] - ±20 mA

IO output current −0.5 V < VO < VCC + 0.5 V

standard outputs - ±25 mA

bus driver outputs - ±35 mA

ICC supply current

standard outputs - 50 mA

bus driver outputs - 70 mA

IGND ground current

standard outputs −50 - mA

bus driver outputs −70 - mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation Tamb = −40 °C to +125 °C

DIP20 package [2] - 750 mW

SO20 package [3] - 500 mW

(T)SSOP20 package [4] - 500 mW

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[2] Ptot derates linearly at 12 mW/K above 70 °C.

[3] Ptot derates linearly at 8 mW/K above 70 °C.

[4] Ptot derates linearly at 5.5 mW/K above 60 °C.

8. Recommended operating conditions

9. Static characteristics

Table 5. Recommended operating conditionsVoltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 74HC299 74HCT299 Unit

Min Typ Max Min Typ Max

VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V

VI input voltage 0 - VCC 0 - VCC V

VO output voltage 0 - VCC 0 - VCC V

Tamb ambient temperature −40 - +125 −40 - +125 °C

∆t/∆V input transition rise and fall rate

VCC = 2.0 V - - 625 - - - ns/V

VCC = 4.5 V - 1.67 139 - 1.67 1.39 ns/V

VCC = 6.0 V - - 83 - - - ns/V

Table 6. Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C −40 °C to+85 °C

−40 °C to+125 °C

Unit

Min Typ Max Min Max Min Max

74HC299

VIH HIGH-levelinput voltage

VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

VIL LOW-levelinput voltage

VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V

VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

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VOH HIGH-leveloutput voltage

VI = VIH or VIL

all outputs

IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

standard outputs

IO = −4.0 mA;VCC = 4.5 V

3.98 4.32 - 3.84 - 3.7 - V

IO = −5.2 mA;VCC = 6.0 V

5.48 5.81 - 5.34 - 5.2 - V

bus driver outputs

IO = −6.0 mA;VCC = 4.5 V

3.98 4.32 - 3.84 - 3.7 - V

IO = −7.8 mA;VCC = 6.0 V

5.48 5.81 - 5.34 - 5.2 - V

VOL LOW-leveloutput voltage

VI = VIH or VIL

all outputs

IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V

IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V

standard outputs

IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

bus driver outputs

IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

II input leakagecurrent

VI = VCC or GND;VCC = 6.0 V

- - ±0.1 - ±1.0 - ±1.0 µA

IOZ OFF-state outputcurrent

VI = VIH or VIL; VO = VCC orGND; VCC = 6.0 V

- - ±0.5 - ±5.0 - ±10.0 µA

ICC supply current VI = VCC or GND; IO = 0 A;VCC = 6.0 V

- - 8.0 - 80 - 160 µA

CI input capacitance - 3.5 - - - - - pF

CI/O input/outputcapacitance

- 10 - - - - - pF

CPD power dissipationcapacitance

per package [1] - 120 - - - - - pF

74HCT299

VIH HIGH-levelinput voltage

VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V

Table 6. Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).


−40 °C to+125 °C

Unit


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[1] CPD is used to determine the dynamic power dissipation (PD in µW).

PD = CPD × VCC2 × fi + ∑(CL × VCC

2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

VIL LOW-levelinput voltage

VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V

VOH HIGH-leveloutput voltage

VI = VIH or VIL; VCC = 4.5 V

all outputs

IO = −20 µA 4.4 4.5 - 4.4 - 4.4 - V

standard outputs

IO = −4.0 mA 3.98 4.32 - 3.84 - 3.7 - V

bus driver outputs

IO = −6.0 mA 3.98 4.32 - 3.84 - 3.7 - V

VOL LOW-leveloutput voltage

VI = VIH or VIL; VCC = 4.5 V

all outputs

IO = 20 µA - 0 0.1 - 0.1 - 0.1 V

standard outputs

IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V

bus driver outputs

IO = 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V

II input leakagecurrent

VI = VCC or GND;VCC = 5.5 V

- - ±0.1 - ±1.0 - ±1.0 µA

IOZ OFF-state outputcurrent

VI = VIH or VIL; VO = VCC orGND per input pin; otherinputs at VCC or GND;IO = 0 A; VCC = 5.5 V

- - ±0.5 - ±5.0 - ±10.0 µA

ICC supply current VI = VCC or GND; IO = 0 A;VCC = 5.5 V

- - 8.0 - 80 - 160 µA

∆ICC additional supplycurrent

per input pin;VI = VCC − 2.1 V;other inputs at VCC orGND; IO = 0 A;VCC = 4.5 V to 5.5 V

I/On, DSR, DSL, MRand S1

- 25 90 - 112.5 - 122.5 µA

CP, S0 - 60 216 - 270 - 294 µA

OEn - 30 108 - 135 - 147 µA

CI input capacitance - 3.5 - - - - - pF

CI/O input/outputcapacitance

- 10 - - - - - pF

CPD power dissipationcapacitance

per package [1] - 125 - - - - - pF

Table 6. Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).


−40 °C to+125 °C

Unit


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∑(CL × VCC2 × fo) = sum of outputs.

CL = output load capacitance in pF;

VCC = supply voltage in V;

VI = GND to VCC for 74HC299;

VI = GND to (VCC − 1.5 V) for 74HCT299.

10. Dynamic characteristics

Table 7. Dynamic characteristicsGND (ground = 0 V); for test circuit, see Figure 11.


−40 °C to+125 °C

Unit


74HC299

tpd propagationdelay

CP to Q0, Q7; see Figure 7 [1]

VCC = 2.0 V - 66 200 - 250 - 300 ns

VCC = 4.5 V - 24 40 - 50 - 60 ns

VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns

VCC = 6.0 V - 19 34 - 43 - 51 ns

CP to I/On; see Figure 7

VCC = 2.0 V - 66 200 - 250 - 300 ns

VCC = 4.5 V - 24 40 - 50 - 60 ns

VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns

VCC = 6.0 V - 19 34 - 43 - 51 ns

MR to Q0, Q7 or I/On;see Figure 8

[2]

VCC = 2.0 V - 66 200 - 250 - 300 ns

VCC = 4.5 V - 24 40 - 50 - 60 ns

VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns

VCC = 6.0 V - 19 34 - 43 - 51 ns

tt transition time bus driver (I/On); see Figure 7 [3]

VCC = 2.0 V - 14 60 - 75 - 90 ns

VCC = 4.5 V - 5 12 - 15 - 18 ns

VCC = 6.0 V - 4 10 - 13 - 15 ns

standard (Q0, Q7); see Figure 7

VCC = 2.0 V - 19 75 - 95 - 110 ns

VCC = 4.5 V - 7 15 - 19 - 22 ns

VCC = 6.0 V - 6 13 - 16 - 19 ns

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tW pulse width CP HIGH or LOW; see Figure 7

VCC = 2.0 V 80 17 - 100 - 120 - ns

VCC = 4.5 V 16 6 - 20 - 24 - ns

VCC = 6.0 V 14 5 - 17 - 20 - ns

MR LOW; see Figure 8

VCC = 2.0 V 80 19 - 100 - 120 - ns

VCC = 4.5 V 16 7 - 20 - 24 - ns

VCC = 6.0 V 14 6 - 17 - 20 - ns

tPZH OFF-state toHIGHpropagationdelay

OEn to I/On; see Figure 10 [4]

VCC = 2.0 V - 50 155 - 195 - 235 ns

VCC = 4.5 V - 18 31 - 39 - 47 ns

VCC = 6.0 V - 14 26 - 33 - 40 ns

tPZL OFF-state toLOWpropagationdelay

OEn to I/On; see Figure 10

VCC = 2.0 V - 41 130 - 165 - 195 ns

VCC = 4.5 V - 15 26 - 33 - 39 ns

VCC = 6.0 V - 12 22 - 28 - 33 ns

tPHZ HIGH toOFF-statepropagationdelay


VCC = 2.0 V - 66 185 - 230 - 280 ns

VCC = 4.5 V - 24 37 - 46 - 56 ns

VCC = 6.0 V - 19 31 - 39 - 48 ns

tPLZ LOW toOFF-statepropagationdelay


VCC = 2.0 V - 55 155 - 195 - 235 ns

VCC = 4.5 V - 20 31 - 39 - 47 ns

VCC = 6.0 V - 16 26 - 33 - 40 ns

trec recovery time MR to CP; see Figure 8

VCC = 2.0 V 5 −14 - 5 - 5 - ns

VCC = 4.5 V 5 −5 - 5 - 5 - ns

VCC = 6.0 V 5 −4 - 5 - 5 - ns

Table 7. Dynamic characteristics …continuedGND (ground = 0 V); for test circuit, see Figure 11.


−40 °C to+125 °C

Unit


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tsu set-up time DSR, DSL to CP; see Figure 7

VCC = 2.0 V 100 33 - 125 - 150 - ns

VCC = 4.5 V 20 12 - 25 - 30 - ns

VCC = 6.0 V 17 10 - 21 - 26 - ns

S0, S1 to CP; see Figure 9

VCC = 2.0 V 100 33 - 125 - 150 - ns

VCC = 4.5 V 20 12 - 25 - 30 - ns

VCC = 6.0 V 17 10 - 21 - 26 - ns

I/On to CP; see Figure 7

VCC = 2.0 V 125 39 - 155 - 190 - ns

VCC = 4.5 V 25 14 - 31 - 38 - ns

VCC = 6.0 V 21 11 - 26 - 32 - ns

th hold time I/On, DSR, DSL to CP;see Figure 7

VCC = 2.0 V 0 −14 - 0 - 0 - ns

VCC = 4.5 V 0 −5 - 0 - 0 - ns

VCC = 6.0 V 0 −4 - 0 - 0 - ns


VCC = 2.0 V 0 −28 - 0 - 0 - ns

VCC = 4.5 V 0 −10 - 0 - 0 - ns

VCC = 6.0 V 0 −8 - 0 - 0 - ns

fmax maximumfrequency

CP input; see Figure 7

VCC = 2.0 V 5.0 15 - 4.0 - 3.4 - MHz

VCC = 4.5 V 25 45 - 20 - 17 - MHz

VCC = 5.0 V; CL = 15 pF - 50 - - - - - MHz

VCC = 6.0 V 29 54 - 24 - 20 - MHz

74HCT299

tpd propagationdelay

CP to Q0, Q7; see Figure 7 [1]

VCC = 4.5 V - 22 37 - 46 - 56 ns

VCC = 5.0 V; CL = 15 pF - 19 - - - - - ns

CP to I/On; see Figure 7

VCC = 4.5 V - 22 37 - 46 - 56 ns

VCC = 5.0 V; CL = 15 pF - 19 - - - - - ns

MR to Q0, Q7 or I/On;see Figure 8

[2]

VCC = 4.5 V - 27 46 - 58 - 69 ns

VCC = 5.0 V; CL = 15 pF - 23 - - - - - ns



−40 °C to+125 °C

Unit


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[1] tpd is the same as tPHL and tPLH.

[2] tpd is the same as tPHL.

[3] tt is the same as tTHL and tTLH.

[4] ten is the same as tPZH and tPZL.

[5] tdis is the same as tPHZ and tPLZ.

tt transition time bus driver (I/On); see Figure 7 [3]

VCC = 4.5 V - 5 12 - 15 - 18 ns

standard (Q0, Q7); see Figure 7

VCC = 4.5 V - 7 15 - 19 - 22 ns

tW pulse width clock HIGH or LOW; see Figure 7

VCC = 4.5 V 20 10 - 25 - 30 - ns

master reset LOW; see Figure 8

VCC = 4.5 V 20 11 - 25 - 30 - ns

ten enable time OEn to I/On; see Figure 10 [4]

VCC = 4.5 V - 19 30 - 38 - 45 ns

tPHZ HIGH toOFF-statepropagationdelay


VCC = 4.5 V - 24 37 - 46 - 56 ns

tPLZ LOW toOFF-statepropagationdelay


VCC = 4.5 V - 20 32 - 40 - 48 ns

trec recovery time MR to CP; see Figure 8

VCC = 4.5 V 10 2 - 9 - 11 - ns

tsu set-up time I/On, DSR, DSL to CP;see Figure 7

VCC = 4.5 V 25 14 - 31 - 38 - ns


VCC = 4.5 V 32 18 - 40 - 48 - ns

th hold time I/On, DSR, DSL to CP;see Figure 7

VCC = 4.5 V 0 −11 - 0 - 0 - ns


VCC = 4.5 V 0 −17 - 0 - 0 - ns

fmax maximumfrequency

CP input; see Figure 7

VCC = 4.5 V 25 42 - 20 - 17 - MHz

VCC = 5.0 V; CL = 15 pF - 46 - - - - - MHz



−40 °C to+125 °C

Unit


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[6] CPD is used to determine the dynamic power dissipation (PD in µW).

PD = CPD × VCC2 × fi × N + Σ(CL × VCC

2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

Σ(CL × VCC2 × fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching.

11. Waveforms

The shaded areas indicate when the input is permitted to change for predictable output performance.

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 7. Clock pulse to outputs I/On, Q0, Q7 propagation delays, the clock pulse width, the I/On, DSR and DSL toclock pulse set-up and hold times, the output transition times and the maximum clock frequency

001aai462

thtsu

th

tPHL

tTHL tTLH

tW

tPLH

tsu

1/fmax

VM

VM

VM

CP input

VI

GND

VI

GND

VOH

VOL

I/On, DSR, DSLinputs

I/On, Q0, Q7outputs

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Fig 8. The master reset pulse width (LOW), the master reset to outputs I/On, Q0, Q7 propagation delays and themaster reset to clock pulse removal time

001aai463

I/On, Q0, Q7outputs

VM

tPHL

VM

MR input VM

GND

GND

VI

tW

trec

CP input

VOL

VI

VOH


Fig 9. Set-up and hold times from the mode control inputs S0, S1 to the clock pulse

001aai464

I/On, DSR, DSL, Sn inputs

CP input

tsu th

VM

VI

GND

GND

VI

VM

tsu th

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Fig 10. 3-state enable and disable times for OEn inputs

tPLZ

tr tf

tPHZ

outputsdisabled

outputsenabled

outputsenabled

I/On outputLOW to OFFOFF to LOW

I/On outputHIGH to OFFOFF to HIGH

OEn input

VI

GND

VM

VM

10 %

10 %

90 %

90 %

VM

tPZL

tPZH

001aai465

VOH

VOL

VOH

VOL

Table 8. Measurement points

Type Input Output

VI VM VM

74HC299 VCC 0.5VCC 0.5VCC

74HCT299 3 V 1.3 V 1.3 V

Test data is given in Table 9.

Definitions for test circuit:

DUT = Device Under Test.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch

Fig 11. Test circuit for measuring switching times

001aai466

DUT

VCC

VI VO

RT

RL = 1 kΩ

CL50 pF

PULSEGENERATOR DUT

VCC

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Table 9. Test data

Type Input Load S1 position

VI tr, tf CL RL tPHL, tPLH

74HC299 VCC 6 ns 15 pF, 50 pF 1 kΩ open

74HCT299 3 V 6 ns 15 pF, 50 pF 1 kΩ open

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12. Package outline

Fig 12. Package outline SOT163-1 (SO20)

UNITA

max. A1 A2 A3 bp c D (1) E (1) (1)e HE L L p Q Zywv θ

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC JEITA

mm

inches

2.65 0.30.1

2.452.25

0.490.36

0.320.23

13.012.6

7.67.4

1.2710.6510.00

1.11.0

0.90.4 8

0

o

o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.10.4

SOT163-1

10

20

w Mbp

detail X

Z

e

11

1

D

y

0.25

075E04 MS-013

pin 1 index

0.1 0.0120.004

0.0960.089

0.0190.014

0.0130.009

0.510.49

0.300.29

0.05

1.4

0.0550.4190.394

0.0430.039

0.0350.016

0.01

0.25

0.01 0.0040.0430.016

0.01

0 5 10 mm

scale

X

θ

AA1

A2

HE

Lp

Q

E

c

L

v M A

(A )3

A

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

99-12-2703-02-19

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Fig 13. Package outline SOT339-1 (SSOP20)

UNIT A1 A2 A3 bp c D(1) E(1) e HE L L p Q (1)Zywv θ



IEC JEDEC JEITA

mm 0.210.05

1.801.65

0.380.25

0.200.09

7.47.0

5.45.2

0.657.97.6

0.90.7

0.90.5

80

o

o0.131.25 0.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

1.030.63

SOT339-1 MO-15099-12-2703-02-19

X

w M

θ

AA1

A2

bp

D

HE

Lp

Q

detail X

E

Z

e

c

L

v M A

(A )3

A

1 10

20 11

y

0.25

pin 1 index

0 2.5 5 mm

scale

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

Amax.

2

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Fig 14. Package outline SOT146-1 (DIP20)

UNIT Amax.

1 2 b1 c D E e MHL



IEC JEDEC JEITA

mm

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT146-199-12-2703-02-13

A min.

A max. b Z

max.wMEe1

1.731.30

0.530.38

0.360.23

26.9226.54

6.406.22

3.603.05

0.2542.54 7.628.257.80

10.0 8.3

24.2 0.51 3.2

0.0680.051

0.0210.015

0.0140.009

1.0601.045

0.250.24

0.140.12

0.010.1 0.30.320.31

0.390.33

0.0780.17 0.02 0.13

SC-603MS-001

MH

c

(e )1

ME

A

L

seat

ing

plan

e

A1

w Mb1

e

D

A2

Z

20

1

11

10

b

E

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

(1)(1) (1)

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

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Fig 15. Package outline SOT360-1 (TSSOP20)

UNIT A1 A2 A3 bp c D (1) E (2) (1)e HE L L p Q Zywv θ



IEC JEDEC JEITA

mm 0.150.05

0.950.80

0.300.19

0.20.1

6.66.4

4.54.3

0.656.66.2

0.40.3

0.50.2

80

o

o0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.750.50

SOT360-1 MO-15399-12-2703-02-19

w Mbp

D

Z

e

0.25

1 10

20 11

pin 1 index

θ

AA1

A2

Lp

Q

detail X

L

(A )3

HE

E

c

v M A

XA

y

0 2.5 5 mm

scale

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

Amax.

1.1

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13. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT299_3 20080728 Product data sheet - 74HC_HCT299_CNV_2

Modifications: • The format of this data sheet has been redesigned to comply with the new identityguidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Section 3: Ordering information added

• Section 12: Package outline drawings added

• Section 9 “Static characteristics”: Family data added

• Section 11 “Waveforms”: Test circuit added

74HC_HCT299_CNV_2 19970828 Product specification - -

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14. Legal information

14.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product statusinformation is available on the Internet at URL http://www.nxp.com.

14.2 Definitions

Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodifications or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequences ofuse of such information.

Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet is intendedfor quick reference only and should not be relied upon to contain detailed andfull information. For detailed and full information see the relevant full datasheet, which is available on request via the local NXP Semiconductors salesoffice. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate andreliable. However, NXP Semiconductors does not give any representations orwarranties, expressed or implied, as to the accuracy or completeness of suchinformation and shall have no liability for the consequences of use of suchinformation.

Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including withoutlimitation specifications and product descriptions, at any time and withoutnotice. This document supersedes and replaces all information supplied priorto the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expectedto result in personal injury, death or severe property or environmentaldamage. NXP Semiconductors accepts no liability for inclusion and/or use ofNXP Semiconductors products in such equipment or applications andtherefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for thespecified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined inthe Absolute Maximum Ratings System of IEC 60134) may cause permanentdamage to the device. Limiting values are stress ratings only and operation ofthe device at these or any other conditions above those given in theCharacteristics sections of this document is not implied. Exposure to limitingvalues for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are soldsubject to the general terms and conditions of commercial sale, as publishedat http://www.nxp.com/profile/terms, including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case ofany inconsistency or conflict between information in this document and suchterms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpretedor construed as an offer to sell products that is open for acceptance or thegrant, conveyance or implication of any license under any copyrights, patentsor other industrial or intellectual property rights.

14.4 TrademarksNotice: All referenced brands, product names, service names and trademarksare the property of their respective owners.

15. Contact information

For more information, please visit: http://www .nxp.com

For sales office addresses, please send an email to: salesad [email protected]

Document status [1] [2] Product status [3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

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© NXP B.V. 2008. All rights reserved.For more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: [email protected]

Date of release: 28 July 2008

Document identifier: 74HC_HCT299_3

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.

16. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 12 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ordering information . . . . . . . . . . . . . . . . . . . . . 24 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 25 Pinning information . . . . . . . . . . . . . . . . . . . . . . 55.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 56 Functional description . . . . . . . . . . . . . . . . . . . 67 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 68 Recommended operating conditions. . . . . . . . 79 Static characteristics. . . . . . . . . . . . . . . . . . . . . 710 Dynamic characteristics . . . . . . . . . . . . . . . . . 1011 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 1813 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 2214 Legal information. . . . . . . . . . . . . . . . . . . . . . . 2314.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 2314.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2314.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2314.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 2315 Contact information. . . . . . . . . . . . . . . . . . . . . 2316 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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SN54165, SN54LS165A, SN74165, SN74LS165APARALLEL-LOAD 8-BIT SHIFT REGISTERSSDLS062B – OCTOBER 1976 – REVISED JANUARY 2000


The SN54165 and SN74165 devicesare obsolete and are no longer supplied.


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schematics of inputs and outputsEl

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typical shift, load, and inhibit sequences


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switching characteristics, SN54165 and SN74165, VCC = 5 V, TA = 25° C



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switching characteristics, SN54LS165A and SN74LS165A, VCC = 5 V, TA = 25° C




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V1.0 5.1

Capítulo 5.- Dispositivos computacionales

5.1.- Sumador . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2

5.2.- Unidad lógica y aritmética . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4

5.3.- Coprocesador y FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6

5.4.- Referencias del capítulo 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7

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V1.0 5.2

5.- Dispositivos computacionalesLos dispositivos computacionales son aquellos que realizan funciones aritméticas

y lógicas de varios bits en paralelo (4, 8, 16,...) como:

• Funciones aritméticas

< Suma

< Resta

< Multiplicación

< División

• Funciones lógicas

< AND

< NAND

< OR

< NOR

< XOR

< Complemento o Inversión

< Desplazamientos (a derecha y a izquierda)

< Rotaciones

5.1.- Sumador

Un sumador es un dispositivo específico para realizar sumas. La figura 5.1muestra el esquela digital de un sumador de 4 bits. Como puede verse, se trata de undispositivo complejo que contiene 32 elementos básicos (en este caso). Cuando seincrementa el número de bits, esta complejidad crece bastante, lo que hace que seainviable su representación. Es por ello por lo que se utiliza un representación comobloque funcional (figura 5.2) siempre acompañada de la tabla de verdad que define sufuncionamiento (figura 5.3). Estas figuras corresponden al modelo comercial 74F283(ver la referencia).

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V1.0 5.3

Figura 5.1. Esquema digital de un sumador completo de 4 bits.

Figura 5.3 Tabla de verdad del sumador de la figura 5.1.

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V1.0 5.4

Figura 5.2 Sumador como bloque funcional.

5.2.- Unidad lógica y aritmética

Sin embargo, en SBM se utilizan bloque funcionales más complejos denominadosUnidad, Lógica y Aritmética (ULA) como la que se muestra en la figura 5.4 que realizafunciones aritméticas como suma, resta (figura 5.5) y funciones lógicas. Estas dosfiguras corresponden al modelo comercial L4C383 (ver esta referencia) que trabaja condatos de 16 bits.

Observar la complejidad de la circuitería para realizar estas tareas.

Sin embargo, las ULAs que se utilizan en los :P son aún mas complejas puestoque disponen de funciones de desplazamiento y recirculación de bits y otras funcionescomplementarias. Es por ello que en SBM de utiliza un bloque multifuncionaldenominado ULA representado por medio de un símbolo como el de la figura 5.6, enla que por medio de una señales de control se selecciona la función a realizar.

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V1.0 5.5

Figura 5.6. Representación simplificada de unaULA.

Figura 5.4. Esquema digital de una ULA.

Figura 5.5. Funciones de laULA de la figura 5.4.El

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V1.0 5.6

Figura 5.7. Comparativa de tiemposde ejecución entre procesador yprocesador + FPU.

5.3.- Coprocesador y FPU

Los coprocesadores eran dispositivos de cálculo que funcionaban bajo el controlde una UCP. Se trataba de un dispositivo externo al procesador especializado encálculo numérico, más concretamente en punto flotante, lo que se conoce como FPU(Floating Point Unit). Las frases anteriores están en pasado porque hoy no se utilizanlos coprocesadores en este formato. Los procesadores actuales que tienen opcionesde cálculo numérico lo hacen por medio de ULAs o FPUs integradas en el propioprocesador.

Sin embargo no deja de ser interesante saber cómo son las FPUs anque seanantiguas ya que su principio es el mismo actualmente.

En todos los casos de cálculo, un procesador con una ULA puede realizar todaslas funciones de una FPU. Sin embargo el éxito deestas unidades lo podemos ver en la figura 5.7que hace una comparativa en cuanto a velocidadde proceso (o su inverso, tiempo de ejecución)entre un procesador (8086) y el mismo procesadorcon FPU (8086 + 8087).

En esta figura se puede ver que una simplesuma es casi 100 veces más rápida cuanto hayFPU, lo que significa un incremento porcentual dela velocidad de proceso del 10.000%.

Si observamos el tiempo de cálculo de unaraíz cuadrada, la relación de tiempos es de 544veces más rápido con FPU.

Las FPUs tienen una arquitectura similar auna UCP, como puede verse en la referencia8087.El

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V1.0 5.7


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Philips Semiconductors Product specification

74F2834-bit binary full adder with fast carry

21989 Mar 03 853-0364 95944

FEATURES• High speed 4-bit addition

• Cascadable in 4-bit increments

• Fast Internal carry look-ahead

DESCRIPTIONThe 74F283 adds two 4-bit binary words (An plus Bn) plus theincoming carry. The binary sum appears on the sum outputs(Σ0–Σ3) and the outgoing carry (COUT) according to the equation:CIN+20(A0+B0)+21(A1+B1)+22(A2+B2)+23(A3+B3)=Σ0+2Σ1+4Σ2+8Σ3+16COUTwhere (+)=plus

Due to the symmetry of the binary add function, the 74F283 can beused with either all active-High operands (positive logic) or with allactive-Low operands (negative logic). See Function Table. In case ofall active-Low operands (negative logic) the results Σ1–Σ4 and COUTshould be interpreted also as active-Low. With active-High inputs,CIN cannot be left open; it must be held Low when no “carry in” isintended. Interchanging inputs of equal weight does not affect theoperation, thus A0, B0, CIN can arbitrarily be assigned to pins 5, 6,7, etc.

Due to pin limitations, the intermediate carries of the 74F283 are notbrought out for use as inputs or outputs. However, other means canbe used to effectively insert a carry into, or bring a carry out from, anintermediate stage.

PIN CONFIGURATION

7

14

13

12

11

10

9

6

5

4

3

2

1 VCC

B2

A3

B3

COUT

A0

B1

B0

Σ1

GND

A1

Σ0

SF00852

Σ3

Σ2

CIN

A2

8

16

15

TYPETYPICAL

PROPAGATIONDELAY

TYPICALSUPPLY CURRENT

(TOTAL)

74F283 6.5ns 40mA


DESCRIPTIONCOMMERCIAL RANGE

VCC = 5V ±10%,Tamb = 0°C to +70°C

PKG DWG #

16-pin plastic DIP N74F283N SOT38-4

16-pin plastic SO N74F283D SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION 74F(U.L.)HIGH/LOW

LOAD VALUEHIGH/LOW

A0 - A3 A operand inputs 1.0/2.0 20µA/1.2mA

B0 - B3 B operand inputs 1.0/2.0 20µA/1.2mA

CIN Carry input 1.0/1.0 20µA/0.6mA

COUT Carry output 50/33 1.0mA/20mA

Σ0–Σ3 Sum outputs 50/33 1.0mA/20mA

NOTE:One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

5 6 3 2 14 15 12 11

4 1

Σ1Σ0

A0 B0 A1 B1 A2 B2 A3 B3

SF00853

13 10

Σ3Σ2

97 CIN COUT

VCC=Pin 16GND=Pin 8

LOGIC SYMBOL (IEEE/IEC)

5

3

14

12

6

2

15

11

7

10

9

Σ

Σ

SF00854

13

1

4

COCI

0

3

0

3

P

Q

0

3

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1989 Mar 03 3

LOGIC DIAGRAM

Σ3

9

10

13

1

4

11

12

15

14

2

3

6

5

7

B3

A3

B2

A2

B1

A1

B0

A0

CIN

COUT

Σ2

Σ1

Σ0

VCC=Pin 16GND=Pin 8 SF00855

FUNCTION TABLE

PINS CIN A0 A1 A2 A3 B0 B1 B2 B3 Σ0 Σ1 Σ2 Σ3 COUT Example:1001

Logic levels L L H L H H L L H H H L L H1001101010011

Active High 0 0 1 0 1 1 0 0 1 1 1 0 0 1 10011(10+9=19)

Active Low 1 1 0 1 0 0 1 1 0 0 0 1 1 0(10+9=19)(carry+5+6=12)

H = High voltage levelL = Low voltage level

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1989 Mar 03 4

Figure A shows how to make a 3-bit adder. Tying the operand inputsof the fourth adder (A3, B3) Low makes Σ3 dependent only on, andequal to, the carry from the third adder. Using somewhat the sameprinciple, Figure B shows a way of dividing the 74F283 into a 2-bitand a 1-bit adder. The third stage adder (A2, B2, Σ2) is used asmeans of getting a carry (C10) signal into the fourth stage adder (viaA2 and B2) and bringing out the carry from the second stage on Σ2.Note that as long as A2 and B2 are the same, whether High or Low,

they do not influence Σ2. Similarly, when A2 and B2 are the same,the carry into the third stage does not influence the carry out of thethird stage. Figure C shows a method of implementing a 5-inputencoder where the inputs are equally weighted. The outputs Σ0, Σ1and Σ2 present a binary number of inputs I0–I4 that are true. Figure D shows one method of implementing a 5-input majority gate.When three or more of the inputs I0–I4 are true, the output M4 istrue.

APPLICATIONS

Σ1Σ0

A0 B0 A1 B1 A2 B2 A3 B3

SF00856

Σ3Σ2

CIN COUT

L

C3

A. 3-bit Adder

Σ1Σ0

A0 B0 A1 B1 A2 B2 A3 B3

Σ3Σ2

CIN COUT

B. 2-bit and 1-bit Adder

CIN C11

A0 B0 A1 B1

C10

A10 B10

Σ1Σ0 Σ10C2

Σ1Σ0

A0 B0 A1 B1 A2 B2 A3 B3

Σ3Σ2

CIN COUT

C. 5-input Encoder

Σ1Σ0

A0 B0 A1 B1 A2 B2 A3 B3

Σ3Σ2

CIN COUT

D. 5-input Majority Gate

I0 I1

I2

I3 I4

20 21 22

I0 I1

I2

I3 I4L

M4

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1989 Mar 03 5

ABSOLUTE MAXIMUM RATINGS(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over theoperating free-air temperature range.)

SYMBOL PARAMETER RATING UNIT

VCC Supply voltage –0.5 to +7.0 V

VIN Input voltage –0.5 to +7.0 V

IIN Input current –30 to +5 mA

VOUT Voltage applied to output in High output state –0.5 to VCC V

IOUT Current applied to output in Low output state 40 mA

Tamb Operating free-air temperature range 0 to +70 °C

Tstg Storage temperature –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETERLIMITS

UNITSYMBOL PARAMETERMin Nom Max

UNIT

VCC Supply voltage 4.5 5.0 5.5 V

VIH High-level input voltage 2.0 V

VIL Low-level input voltage 0.8 V

IIK Input clamp current –18 mA

IOH High-level output current –1 mA

IOL Low-level output current 20 mA

Tamb Operating free-air temperature range 0 70 °C

DC ELECTRICAL CHARACTERISTICS(Over recommended operating free-air temperature range unless otherwise noted.)

NO TAGLIMITS

SYMBOL PARAMETER TEST CONDITIONSNO TAGMIN TYP

NO TAG MAXUNIT

VO High level output voltageVCC = MIN, VIL = MAX ±10%VCC 2.5

VVOH High-level output voltageVIH = MIN, IOH = MAX ±5%VCC 2.7 3.4

V

VO Low level output voltageVCC = MIN, VIL = MAX ±10%VCC 0.30 0.50

VVOL Low-level output voltageVIH = MIN, IOL = MAX ±5%VCC 0.30 0.50

V

VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V

II Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA

IIH High-level input current VCC = MAX, VI = 2.7V 20 µA

I Low level input currentCIN only

VCC = MAX V = 0 5V–0.6 mA

IIL Low-level input currentAn, Bn

VCC = MAX, VI = 0.5V–1.2 mA

IOS Short-circuit output currentNO TAG VCC = MAX –60 –150 mA

ICC Supply current (total)4 VCC = MAX 40 55 mA

NOTES:1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.2. All typical values are at VCC = 5V, Tamb = 25°C.3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shortingof a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In anysequence of parameter tests, IOS tests should be performed last.

4. ICC should be measured with all outputs open and the following conditions:Condition1: all inputs groundedCondition 2: all B inputs Low, other inputs at 4.5VCondition 3: all inputs at 4.5V

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1989 Mar 03 6

AC ELECTRICAL CHARACTERISTICS

LIMITS

TESTTamb= +25°CV = +5 V

Tamb = 0°C to +70°CV = +5 V ± 10%SYMBOL PARAMETER TEST

CONDITIONSVCC = +5.VCL = 50pF,

VCC = +5.V ± 10%CL = 50pF, UNIT

CONDITIONS CL = 50pF,RL = 500Ω

CL = 50pF, RL = 500Ω

MIN TYP MAX MIN MAX

tPLHtPHL

Propagation delayCIN to Σi Waveform 1, 2 3.5

4.07.07.0

9.59.5

3.03.5

10.510.5

nsns

tPLHtPHL

Propagation delayAi or Bi to Σi Waveform 1, 2 3.5

3.57.07.0

9.59.5

2.53.5

10.510.5

nsns

tPLHtPHL

Propagation delayCIN to COUT

Waveform 2 3.53.0

5.75.4

7.57.0

3.52.5

8.58.0

nsns

tPLHtPHL

Propagation delayAi or Bi to COUT

Waveform 1, 2 3.52.5

5.75.3

7.57.0

3.02.5

8.58.0

nsns

AC WAVEFORMSFor all waveforms, VM=1.5V.

VM

VM VM

VMAi, Bi, CIN

Σi, COUT

tPLH

SF00857

tPHL

Waveform 1. Propagation Delay Operands and Carry Inputs to Outputs

VM

VM VM

VM

tPHL tPLH

SF00858

Ai, Bi, CIN

Σi, COUT

Waveform 2. Propagation DelayOperands and Carry Inputs to Outputs

TEST CIRCUIT AND WAVEFORM

tw 90%

VM10%

90%

VM10%

90%

VM10%

90%

VM10%

NEGATIVEPULSE

POSITIVEPULSE

tw

AMP (V)

0V

0V

tTHL (tf )

INPUT PULSE REQUIREMENTS

rep. rate tw tTLH tTHL

1MHz 500ns 2.5ns 2.5ns

Input Pulse Definition

VCC

family

74F

D.U.T.PULSEGENERATOR

RLCLRT

VIN VOUT

Test Circuit for Totem-Pole Outputs

DEFINITIONS:RL = Load resistor;

see AC ELECTRICAL CHARACTERISTICS for value.CL = Load capacitance includes jig and probe capacitance;

see AC ELECTRICAL CHARACTERISTICS for value.RT = Termination resistance should be equal to ZOUT of

pulse generators.

tTHL (tf )

tTLH (tr )

tTLH (tr )

AMP (V)

amplitude

3.0V 1.5V

VM

SF00006

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DEVICES INCORPORATED

L4C383

16-bit Cascadable ALU (Extended Set)

Arithmetic Logic Units08/16/2000–LDS.383-E1

High-Speed (15ns), Low Power16-bit Cascadable ALU Extended Function Set(32 Advanced ALU Functions) All Registers Have a Bypass Pathfor Complete Flexibility Replaces IDT7383 68-pin PLCC, J-Lead

FEATURES DESCRIPTION

L4C38316-bit Cascadable ALU (Extended Set)DEVICES INCORPORATED

L4C383 BLOCK DIAGRAM

The L4C383 is a flexible, high speed,cascadable 16-bit Arithmetic and LogicUnit. The L4C383 is capable ofperforming up to 32 differentarithmetic or logic functions.The L4C383 can be cascaded to perform32-bit or greater operations. See“Cascading the L4C383” on the nextpage.ARCHITECTUREThe L4C383 operates on two 16-bitoperands (A and B) and produces a 16-

bit result (F). Five select lines controlthe ALU and provide 19 arithmetic and13 logical functions. Registers areprovided on both the ALU inputs andthe output, but these may be bypassedunder user control. An internal feed-back path allows the registered ALUoutput to be routed to one or both ofthe ALU inputs, accommodating chainoperations and accumulation.ALU OPERATIONSThe S4–S0 lines specify the operation tobe performed. The ALU functions andtheir select codes are shown in Table 1.ALU STATUSThe ALU provides Overflow and Zerostatus bits. A Carry output is alsoprovided for cascading multipledevices, however it is only defined forthe 19 arithmetic functions. The ALUsets the Zero output when all 16 outputbits are zero. The N, C16 and OVF flagsfor the arithmetic operations aredefined in Table 2.OPERAND REGISTERSThe L4C383 has two 16-bit wide inputregisters for operands A and B. Theseregisters are rising edge triggered by acommon clock. The A register isenabled for input by setting the ENAcontrol LOW, and the B register isenabled for input by setting the ENBcontrol LOW. When either the ENAcontrol or ENB control is HIGH, thedata in the corresponding input registerwill not change.This architecture allows the L4C383 toaccept arguments from a single 16-bitdata bus. For those applications that donot require registered inputs, both theA and B operand registers can bebypassed with the FTAB control line.

A REGISTER B REGISTER

ALU

RESULT REGISTER

A15-A0 B15-B0

F15-F0

FFFFH FFFFH

ENB

FTAB

S4-0

N, C16

OVF, Z

ENF

FTF

OE

CLK

ENA

16 16

5

4

16

16

16

TO ALL REGISTERS

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L4C383



OUTPUT REGISTERThe output of the ALU drives the input ofa 16-bit register. This rising-edge-triggered register is clocked by the sameclock as the input registers. When theENF control is LOW, data from the ALUwill be clocked into the output register.By disabling the output register, interme-diate results can be held while loadingnew input operands. Three-state driverscontrolled by the OE input allow theL4C383 to be configured in a singlebidirectional bus system.The output register can be bypassed byasserting the FTF control signal (FTF =HIGH). When the FTF control is asserted,output data is routed around the outputregister, however, it continues to functionnormally via the ENF control. Thecontents of the output register will againbe available on the output pins if FTF isreleased.CASCADING THE L4C383Cascading the L4C383 to 32 bits isaccomplished simply by connecting theC16 output of the least significant slice tothe C0 input of the most sig-nificant slice.The S4-S0, ENA, ENB, and ENF lines are

When the FTAB control is asserted(FTAB = HIGH), data is routedaround the A and B input registers;however, they continue to functionnormally via the ENA and ENBcontrols. The contents of the inputregisters will again be available to theALU if the FTAB control is released.

S4-S0 FUNCTION

00000 A + B + C0

00001 A OR B

00010 A + B + C0

00011 A + B + C0

00100 A + C0

00101 A OR F

00110 A – 1 + C0

00111 A + C0

01000 A + F + C0

01001 A OR F

01010 A + F + C0

01011 A + F + C0

01100 F + B + C0

01101 A OR B

01110 F + B + C0

01111 F + B + C0

10000 A XOR B

10001 A AND B

10010 A AND B

10011 A XNOR B

10100 A XOR F

10101 A AND F

10110 A AND F

10111 ALL 1's + C0

11000 B + C0

11001 A AND B

11010 B + C0

11011 B – 1 + C0

11100 F + C0

11101 A OR B

11110 F – 1 + C0

11111 F + C0

TABLE 1. ALU FUNCTIONS

Bit Carry Generate = gi = AiBi for i = 0 ... 15Bit Carry Propagate = pi = Ai + Bi for i = 0 ... 15

P0 = p0

Pi = pi (Pi–1) for i = 1 ... 15

and

G0 = g0

Gi = gi + pi (Gi–1) for i = 1 ... 15Ci = Gi–1 + Pi–1 (C0) for i = 1 ... 15

then

C16 = G15 + P15C0

OVF = C15 XOR C16

Zero = All Output Bits Equal ZeroN = Sign Bit of ALU Operation

TABLE 2. ALU STATUS FLAGS

common to both devices. The Zero outputflags should be logically ANDed toproduce the Zero flag for the 32-bit result.The OVF and C16 outputs of the mostsignificant slice are valid for the 32-bitresult.Propagation delay calculations for thisconfiguration require two steps: Firstdetermine the propagation delay from theinput of interest to the C16 output of thelower slice. Add this number to the delayfrom the C0 input of the upper slice to theoutput of interest (of the C0 setup time, ifthe F register is used). The sum gives theoverall input-to-output delay (or setuptime) for the 32-bit configuration. Thismethod gives a conservative result, sincethe C16 output is very lightly loaded.Formulas for calculation of all criticaldelays for a 32-bit system are shown inFigures 4A through 4D.Cascading to greater than 32 bits can beaccomplished by simply connecting theC16 output of each slice to the C0 input ofthe next more significant slice.Propagation delays are calculated asfor the 32-bit case, except that the C0to C16 delays for all intermediate slicesmust be added to the overall delay foreach path.

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From To Calculated Specification LimitClock F = Same as 16-bit caseClock Other = (Clock C16) + (C0 Out)C0 Other = (C0 C16) + (C0 Out)S4-S0 Other = (S4-S0 C16) + (C0 Out)A, B Setup time = Same as 16-bit caseC0 Setup time = (C0 C16) + (C0 Setup time)S4-S0 Setup time = (S4-S0 C16) + (C0 Setup time)ENA, ENB, ENF Setup time = Same as 16-bit caseMinimum cycle time = (Clock C16) + (C0 Setup time)

FIGURE 4B. FTAB = 0, FTF = 1

From To Calculated Specification LimitClock F = (Clock C16) + (C0 F)Clock Other = (Clock C16) + (C0 Out)C0 F = (C0 C16) + (C0 F)C0 Other = (C0 C16) + (C0 Out)S4-S0 F = (S4-S0 C16) + (C0 F)S4-S0 Other = (S4-S0 C16) + (C0 Out)A, B Setup time = Same as 16-bit caseC0 Setup time = (C0 C16) + (C0 Setup time)S4-S0 Setup time = (S4-S0 C16) + (C0 Setup time)ENA, ENB, ENF Setup time = Same as 16-bit caseMinimum cycle time = (Clock C16) + (C0 Setup time)

D

16

Q

A31-A16

A

F

BC0

D

16

Q

A

F

BC0

CLOCK

MOSTSIGNIFICANT

SLICE

LEASTSIGNIFICANTSLICE

S 0–S4C0,

C16

DQ

DQ

B31-B16

F31-F16

A15-A0 B15-B0

F15-F0

FIGURE 4A. FTAB = 0, FTF = 0

D

16

Q

DQ

A31-A16

A

F

BC0

D

16

Q

DQ

A

F

BC0

CLOCK CLOCK

CLOCK

MOSTSIGNIFICANT

SLICE


S 0–S4C0,

C16

DQ

DQ

B31-B16

F31-F16

A15-A0 B15-B0

F15-F0

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FIGURE 4C. FTAB = 1, FTF = 0

From To Calculated Specification LimitClock F = Same as 16-bit caseA, B Other = (A, B C16) + (C0 Out)C0 Other = (C0 C16) + (C0 Out)S4-S0 Other = (S4-S0 C16) + (C0 Out)A, B Setup time = (A, B C16) + (C0 Setup time)C0 Setup time = (C0 C16) + (C0 Setup time)S4-S0 Setup time = (S4-S0 C16) + (C0 Setup time)ENA, ENB, ENF Setup time = Same as 16-bit caseMinimum cycle time = (Clock C16) + (C0 Setup time)(F register accumulate loop)

FIGURE 4D. FTAB = 1, FTF = 1

From To Calculated Specification LimitA, B F = (A, B C16) + (C0 F)A, B Other = (A, B C16) + (C0 Out)C0 F = (C0 C16) + (C0 F)C0 Other = (C0 C16) + (C0 Out)S4-S0 F = (S4-S0 C16) + (C0 F)S4-S0 Other = (S4-S0 C16) + (C0 Out)A, B Setup time = (A, B C16) + (C0 Setup time)C0 Setup time = (C0 C16) + (C0 Setup time)S4-S0 Setup time = (S4-S0 C16) + (C0 Setup time)ENA, ENB, ENF Setup time = Same as 16-bit caseMinimum cycle time = (Clock C16) + (C0 Setup time)(F register accumulate loop)

16

DQ

A31-A16

A

F

BC0

16

DQ

A

F

BC0

CLOCK CLOCK

MOSTSIGNIFICANT

SLICE


S 0–S4C0,

C16

B31-B16

F31-F16

A15-A0 B15-B0

F15-F0

16

A31-A16

A

F

BC0

16

A

F

BC0

MOSTSIGNIFICANT

SLICE


S 0–S4C0,

C16

B31-B16

F31-F16

A15-A0 B15-B0

F15-F0

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L4C383



Symbol Parameter Test Condition Min Typ Max Unit

VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V

VOL Output Low Voltage VCC = Min., IOL = 8.0 mA 0.5 V

VIH Input High Voltage 2.0 VCC V

VIL Input Low Voltage (Note 3) 0.0 0.8 V

IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±20 µA

IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA

ICC1 VCC Current, Dynamic (Notes 5, 6) 15 30 mA

ICC2 VCC Current, Quiescent (Note 7) 1.5 mA

Storage temperature ........................................................................................................... –65°C to +150°C

Operating ambient temperature ........................................................................................... –55°C to +125°C

VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V

Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V

Output current into low outputs ............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)

OPERATING CONDITIONS To meet specified electrical and switching characteristics

ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)

Mode Temperature Range (Ambient) Supply VoltageActive Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V

Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V

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L4C383



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1234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890123456789012345678901234567890121234567890123456789012345678901234567890123456789012123456789012345678901234567890123456789012345678901212345678901234567890

L4C383-55*

F15-F0 N OVF, Z C16

32 38 53 36

— — 34 22

— 42 42 42

56 38 53 36

37 — 34 22

55 42 42 42

— 36 46 37

32 — — —

— — 34 22

— 42 42 42

55 36 46 37

56 38 53 36

37 — 34 22

55 42 42 42

SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)

GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes 9, 10 (ns)

To Output

From Input

FTAB = 0, FTF = 0

Clock

C0

S4-S0

FTAB = 0, FTF = 1

Clock

C0

S4-S0

FTAB = 1, FTF = 0

A15-A0, B15-B0

Clock

C0

S4-S0

FTAB = 1, FTF = 1

A15-A0, B15-B0

Clock

C0

S4-S0

Input

A15-A0, B15-B0

C0

S4-S0

ENA, ENB, ENF

GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)

L4C383-40*

FTAB = 0 FTAB = 1

Setup Hold Setup Hold

8 2 28 2

16 0 16 0

32 0 32 0

10 2 10 2

L4C383-26

FTAB = 0 FTAB = 1


8 2 16 2

8 0 8 0

18 0 18 0

8 2 8 2

L4C383-55*

FTAB = 0 FTAB = 1


8 2 35 2

21 0 21 0

44 0 44 0

10 2 10 2

TRI-STATE ENABLE /DISABLE TIMES Notes 9, 10, 11 (ns)

L4C383-55* L4C383-40* L4C383-26

20 18 16

20 18 16

tENA

tDIS

CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)

Minimum Cycle Time

Highgoing Pulse

Lowgoing Pulse

L4C383-55* L4C383-40* L4C383-26

43 34 20

15 10 10

15 10 10

L4C383-40*

F15-F0 N OVF, Z C16

26 30 44 32

— — 28 20

— 32 34 35

46 30 44 32

30 — 28 20

40 32 34 35

— 30 40 32

26 — — —

— — 28 20

— 32 34 35

40 30 40 32

46 30 44 32

30 — 28 20

40 32 34 35

L4C383-26

F15-F0 N OVF, Z C16

22 22 26 22

— — 18 18

— 22 22 22

28 22 26 22

22 — 18 18

26 22 22 22

— 22 22 22

22 — — —

— — 18 18

— 22 22 22

26 22 22 22

28 22 26 22

22 — 18 18

26 22 22 22

123456789012345678901234123456789012345678901234123456789012345678901234123456789012345678901234*DISCONTINUED SPEED GRADE

Elec

trónic

aDi

gital

Aplic

ada


L4C383



123456789012312345678901231234567890123123456789012312345678901231234567890123123456789012312345678901231234567890123123456789012312345678901231234567890123

L4C383-20 L4C383-15*

8 6

8 6

1234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456

1234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456123456789012345678901234561234567890123456789012345612345678901234567890123456

12345678901231234567890123123456789012312345678901231234567890123123456789012312345678901231234567890123123456789012312345678901231234567890123123456789012312345678901231234567890123123456789012312345678901231234567890123

L4C383-20 L4C383-15*

18 14

5 4

5 4

L4C383-15*

FTAB = 0 FTAB = 1


5 0 12 0

10 0 10 0

12 0 12 0

5 0 5 0

L4C383-15*

F15-F0 N OVF, Z C16

11 15 15 15

— — 13 13

— 14 15 14

15 15 15 15

14 — 13 13

15 14 15 14

— 14 15 14

11 — — —

— — 13 13

— 14 15 14

15 14 15 14

15 15 15 15

14 — 13 13

15 14 15 14

SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)


To Output

From Input

FTAB = 0, FTF = 0

Clock

C0

S4-S0

FTAB = 0, FTF = 1

Clock

C0

S4-S0

FTAB = 1, FTF = 0

A15-A0, B15-B0

Clock

C0

S4-S0

FTAB = 1, FTF = 1

A15-A0, B15-B0

Clock

C0

S4-S0

L4C383-20

F15-F0 N OVF, Z C16

11 20 20 20

— — 14 14

— 18 20 18

20 20 20 20

18 — 14 14

20 18 20 18

— 16 20 17

11 — — —

— — 14 14

— 18 20 18

20 16 20 17

20 20 20 20

18 — 14 14

20 18 20 18

Input

A15-A0, B15-B0

C0

S4-S0

ENA, ENB, ENF


L4C383-20

FTAB = 0 FTAB = 1


5 0 14 0

12 0 12 0

15 0 15 0

5 0 5 0


tENA

tDIS


Minimum Cycle Time

Highgoing Pulse

Lowgoing Pulse123456789012345678901234123456789012345678901234123456789012345678901234123456789012345678901234*DISCONTINUED SPEED GRADE

Elec

trónic

aDi

gital

Aplic

ada


L4C383



1234567890123456789012345678901212345612345678901234567890123456789012123456123456789012345678901234567890121234561234567890123456789012345678901212345612345678901234567890123456789012123456123456789012345678901234567890121234561234567890123456789012345678901212345612345678901234567890123456789012123456123456789012345678901234567890121234561234567890123456789012345678901212345612345678901234567890123456789012123456123456789012345678901234567890121234561234567890123456789012345678901212345612345678901234567890123456789012123456123456789012345678901234567890121234561234567890123456789012345678901212345612345678901234567890123456789012123456

12345678901234567890123456789012123451234567890123456789012345678901212345123456789012345678901234567890121234512345678901234567890123456789012123451234567890123456789012345678901212345123456789012345678901234567890121234512345678901234567890123456789012123451234567890123456789012345678901212345123456789012345678901234567890121234512345678901234567890123456789012123451234567890123456789012345678901212345123456789012345678901234567890121234512345678901234567890123456789012123451234567890123456789012345678901212345

123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234

123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234123456789012345678901234567890121234567890123456789012345678901212345678901234

SWITCHING CHARACTERISTICS — M ILITARY OPERATING RANGE (–55°C to +125°C)


To Output

From Input

FTAB = 0, FTF = 0

Clock

C0

S4-S0

FTAB = 0, FTF = 1

Clock

C0

S4-S0

FTAB = 1, FTF = 0

A15-A0, B15-B0

Clock

C0

S4-S0

FTAB = 1, FTF = 1

A15-A0, B15-B0

Clock

C0

S4-S0

L4C383-30*

F15-F0 N OVF, Z C16

26 28 34 28

— — 22 22

— 28 28 28

34 28 34 28

26 — 22 22

30 28 28 28

— 28 28 28

26 — — —

— — 22 22

— 28 28 28

30 28 28 28

34 28 34 28

26 — 22 22

30 28 28 28

L4C383-45*

F15-F0 N OVF, Z C16

28 34 50 34

— — 32 23

— 38 38 38

56 34 50 34

32 — 32 23

46 38 38 38

— 32 46 36

28 — — —

— — 32 23

— 38 38 38

45 32 46 36

56 34 50 34

32 — 32 23

46 38 38 38

L4C383-65*

F15-F0 N OVF, Z C16

37 44 63 45

— — 42 25

— 48 48 48

68 44 63 45

42 — 42 25

66 48 48 48

— 44 56 44

37 — — —

— — 42 25

— 48 48 48

65 44 56 44

68 44 63 45

42 — 42 25

66 48 48 48

Input

A15-A0, B15-B0

C0

S4-S0

ENA, ENB, ENF


L4C383-45*

FTAB = 0 FTAB = 1


8 3 33 3

20 0 20 0

36 0 36 0

10 2 10 2

L4C383-30*

FTAB = 0 FTAB = 1


8 3 20 3

12 0 12 0

20 0 20 0

10 2 10 2

L4C383-65*

FTAB = 0 FTAB = 1


10 3 43 3

25 0 25 0

50 0 50 0

12 2 12 2


L4C383-65* L4C383-45* L4C383-30*

22 20 18

22 20 18

tENA

tDIS


Minimum Cycle Time

Highgoing Pulse

Lowgoing Pulse

L4C383-65* L4C383-45* L4C383-30*

52 38 26

20 15 12

20 15 12123456789012345678901234123456789012345678901234123456789012345678901234123456789012345678901234*DISCONTINUED SPEED GRADE

Elec

trónic

aDi

gital

Aplic

ada


L4C383



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SWITCHING CHARACTERISTICS — M ILITARY OPERATING RANGE (–55°C to +125°C)


To Output

From Input

FTAB = 0, FTF = 0

Clock

C0

S4-S0

FTAB = 0, FTF = 1

Clock

C0

S4-S0

FTAB = 1, FTF = 0

A15-A0, B15-B0

Clock

C0

S4-S0

FTAB = 1, FTF = 1

A15-A0, B15-B0

Clock

C0

S4-S0

L4C383-25*

F15-F0 N OVF, Z C16

14 24 24 24

— — 18 18

— 22 24 22

25 24 24 24

21 — 18 18

25 22 24 22

— 20 25 22

14 — — —

— — 18 18

— 22 24 22

25 20 25 22

25 24 24 24

21 — 18 18

25 22 24 22

Input

A15-A0, B15-B0

C0

S4-S0

ENA, ENB, ENF


L4C383-20*

FTAB = 0 FTAB = 1


6 2 12 2

12 0 12 0

16 0 16 0

6 0 6 0

L4C383-25*

FTAB = 0 FTAB = 1


7 2 14 2

14 0 14 0

19 0 19 0

7 0 7 0


L4C383-25* L4C383-20*

14 10

14 10

tENA

tDIS


Minimum Cycle Time

Highgoing Pulse

Lowgoing Pulse

L4C383-25* L4C383-20*

20 18

8 6

8 6

L4C383-20*

F15-F0 N OVF, Z C16

14 20 20 20

— — 16 16

— 18 20 18

20 20 20 20

17 — 16 16

20 18 20 18

— 17 20 17

14 — — —

— — 16 16

— 18 20 18

20 17 20 17

20 20 20 20

17 — 16 16

20 18 20 18

123456789012345678901234123456789012345678901234123456789012345678901234123456789012345678901234*DISCONTINUED SPEED GRADE

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L4C383



1. Maximum Ratings indicate stressspecifications only. Functional oper-ation of these products at values beyondthose indicated in the Operating Condi-tions table is not implied. Exposure tomaximum rating conditions for ex-tended periods may affect reliability.2. The products described by this spec-ification include internal circuitry de-signed to protect the chip from damag-ing substrate injection currents and ac-cumulations of static charge. Neverthe-less, conventional precautions shouldbe observed during storage, handling,and use of these circuits in order toavoid exposure to excessive electricalstress values.3. This device provides hard clamping oftransient undershoot and overshoot. In-put levels below ground or above VCCwill be clamped beginning at –0.6 V andVCC + 0.6 V. The device can withstandindefinite operation with inputs in therange of –0.5 V to +7.0 V. Device opera-tion will not be adversely affected, how-ever, input current levels will be well inexcess of 100 mA.4. Actual test conditions may vary fromthose designated but operation is guar-anteed as specified.5. Supply current for a given applica-tion can be accurately approximated by:

whereN = total number of device outputsC = capacitive load per outputV = supply voltageF = clock frequency

6. Tested with all outputs changing ev-ery cycle and no load, at a 5 MHz clockrate.7. Tested with all inputs within 0.1 V ofVCC or Ground, no load.8. These parameters are guaranteedbut not 100% tested.

NCV F4

2

NOTES

9. AC specifications are tested withinput transition times less than 3 ns,output reference levels of 1.5 V (excepttDIS test), and input levels of nominally0 to 3.0 V. Output loading may be aresistive divider which provides forspecified IOH and IOL at an outputvoltage of VOH min and VOL maxrespectively. Alternatively, a diodebridge with upper and lower currentsources of IOH and IOL respectively,and a balancing voltage of 1.5 V may beused. Parasitic capacitance is 30 pFminimum, and may be distributed.This device has high-speed outputs ca-pable of large instantaneous currentpulses and fast turn-on/turn-off times.As a result, care must be exercised in thetesting of this device. The followingmeasures are recommended:a. A 0.1 µF ceramic capacitor should beinstalled between VCC and Groundleads as close to the Device Under Test(DUT) as possible. Similar capacitorsshould be installed between device VCCand the tester common, and deviceground and tester common.b. Ground and VCC supply planesmust be brought directly to the DUTsocket or contactor fingers.c. Input voltages should be adjusted tocompensate for inductive ground and VCCnoise to maintain required DUT inputlevels relative to the DUT ground pin.10. Each parameter is shown as a min-imum or maximum value. Input re-quirements are specified from the pointof view of the external system drivingthe chip. Setup time, for example, isspecified as a minimum since the exter-nal system must supply at least thatmuch time to meet the worst-case re-quirements of all parts. Responses fromthe internal circuitry are specified fromthe point of view of the device. Outputdelay, for example, is specified as amaximum since worst-case operation ofany device always provides data withinthat time.

11. For the tENA test, the transition ismeasured to the 1.5 V crossing pointwith datasheet loads. For the tDIS test,the transition is measured to the±200mV level from the measuredsteady-state output voltage with±10mA loads. The balancing volt-age, VTH, is set at 3.5 V for Z-to-0and 0-to-Z tests, and set at 0 V for Z-to-1 and 1-to-Z tests.12. These parameters are only tested atthe high temperature extreme, which isthe worst case for leakage current.

S1

IOH

IOL

VTHCL

DUT

OE

0.2 V

tDIStENA

0.2 V

1.5 V 1.5 V

3.5V Vth

1 Z

0 Z

Z 1

Z 01.5 V

1.5 V0V Vth

VOL*

VOH*

VOL*VOH*

Measured VOL with IOH = –10mA and IOL = 10mAMeasured VOH with IOH = –10mA and IOL = 10mA

FIGURE B. THRESHOLD LEVELS

FIGURE A. OUTPUT LOADING CIRCUIT

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L4C383



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6768 646510

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

3

TopView

4 66 63 6212

27 32 33 34 35 36 37 38

61

39 40

9

41 42 43

58 67

28 29 30 31

B7

B6

B5

B4

B3

B2

B1

B0

ENAENBFTABS4

S3

S2

S1

S0

C0

A9

A10

A11

A12

A13

A14

A15

CLKVCC

GNDC16

GNDN

ZEROOVFENFFTF

A8

A7

A6

A5

A4

A3

A2

A1

A0

B15

B14

B13

B12

B11

B10

B9

B8

OE

F15

F14

F13

F12

F11

F10 F

9

F8

F7

F6

F5

F4

F3

F2

F1

F0

68-pin


68-pin

0°C to +70°C — C OMMERCIAL SCREENING

Plastic J-Lead Chip Carrier(J2)

L4C383JC26L4C383JC20

Speed

26 ns20 ns

–55°C to +125°C — MIL-STD-883 C OMPLIANT

–55°C to +125°C — C OMMERCIAL SCREENING

A

B

C

D

E

F

G

H

J

K

L

Top View

Through Package

(i.e., Component Side Pinout)

1 2 3 4 5 6 7 8 9 10 11

A8

A9

A11

A13

A15

VCC

C16

N

OVF

OE

F15

A7

A6

F14

F13

A5

A4

F12

F11

A3

A2

F10

F9

A1

A0

F8

F7

B15

B14

F6

F5

B13

B12

F4

F3

B11

B10

F2

F1

B9

B8

B5

B3

B1

ENA

FTAB

S3

S1

C0

F0

A10

A12

A14

CLK

GND

GND

ZERO

ENF

FTF

B7

B6

B4

B2

B0

ENB

S4

S2

S0

Ceramic Pin Grid Array(G1)

Discontinued Package

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V1.0 6.1

Capítulo 6.- Dispositivos de Memoria

6.1.- Clasificación . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2

6.2.- Memoria estática de acceso aleatorio (RAM). . . . . . . . . . . . . . . . . . . . 6.2

6.3.- Memorias dinámicas de acceso aleatorio (DRAM). . . . . . . . . . . . . . . 6.5

6.4.- Memoria de acceso aleatorio de sólo lectura (RMM). . . . . . . . . . . . . . 6.6

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V1.0 6.2

6.1.- Clasificación

Industrialmente existen muchos tipos de memorias que pueden clasificarse segúnvarios criterios. Veamos algunos de ellos.

Tipo de acceso :

• Directo. La información se localiza por medio de un número que sedenomina dirección.

• Asociativo. La localización se hace por medio del contenido o parte de él.

Formato de la información:

• Paralelo. Todos los bits de la información se obtiene simultáneamente en elmismo instante temporal.

• Serie. Los bits de la información se obtienen a lo largo de un periodo detiempo bit a bit.

Almacenamiento:

• Volátil. En este caso la información desaparece cuando cesa la alimentacióndel dispositivo.

• No volátil. La información bo desaparece auque no haya alimentación.

Funcionamiento:

• Estático. La información se mantiene siempre que haya alimentación en eldispositivo.

• Dinámico. Es necesario refrescar la información para mantenerla aún conalimentación en el dispositivo.

Existen otra muchas posibilidades que no se citan aquí ya que este documento solo esuna introducción.

6.2.- Memoria estática de acceso aleatorio (RAM).

El desarrollo de este apartado está realizado en el capítulo 4 del libro “SistemasBasados en Microprocesadores” junto con el capítulo 2 del libro “Diseño Práctico de

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V1.0 6.3

SBMs” (ver la bibliografía).

Sin embargo, con el objetivo de situarnos en dispositivos comerciales, en la figura6.1 se muestra el esquema digital de una memoria de 2Mb.

Este esquema corresponde al modelo CY7C1010DV33 del fabricante Cypress.Como puede verse está organizada en 256 bytes a los que se accede por medio de 18señales de dirección (A17 - A0).

La figura 6.2 muestra los cronogramas funcionales de este dispositivo para el ciclode lectura. El primero de ellos es para el caso en el que las señales /OE y /CE estápermanentemente a nivel bajo. Así podemos ver cuanto es el tiempo de acceso desdelas direcciones. En el segundo, las señales /OE y /CE determinan los parámetrostemporales. En la referencia CY7C1010DV33 se encuentran las tablas con los valoresde las cotas de estos cronogramas.

Figura 6.1. Esquema digital de una memoria RAM estática de 2Mbitsorganizada en 256Kbx8.

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V1.0 6.4

Figura 6.2. Cronogramas del ciclo de lectura.

La figura 6.3 muestra los cronogramas de escritura de este dispositivo. Observadque así como en el ciclo de lectura, el flanco de bajada de la señal /OE o /CE esdesde donde se cuenta el tiempo de lectura, en los ciclos de escritura el dato ha deestar presente un tiempo antes (tSD) y un tiempo después (tHD) del flanco de subidade la señal /WE, respecto al cual se acotan los tiempos.

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V1.0 6.5

Figura 6.3. Cronogramas del ciclo de escritura.

6.3.- Memorias dinámicas de acceso aleatorio (DRAM ).

Las memorias RAM dinámicas (DRAM) forman un grupo muy importante dentrode la memorias electrónicas y deben de ser estudiadas detalladamente debido a sucomplejidad funcional. En el capítulo 4 del el libro “Sistemas Basados enMicroprocesadores” se hace una introducción a los modos básicos de funcionamientode estos dispositivo y su control. Este tipo de memoria es el que se utiliza enordenadores que requieren una alta capacidad de almacenamiento RAM como lpsordenadores personales y superiores. Sin embargo no es frecuente encontrarlas ensistemas industriales de control basados en :C.

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V1.0 6.6

6.4.- Memoria de acceso aleatorio de sólo lectura ( RMM).

RMM (Read Mostly Memory, memorias de lectura principalmente) es el nombregenérico que reciben las memoria conocidas como ROM (Read Only Memory) y PROM(Progammable Read Only Memory). Este último grupo entran una gran variedad dememorias muy dependientes de evolución de la tecnología.

Las RMM tienen dos ciclos funcionales; el de lectura y el de programación. El delectura es totalmente equivalente al de una memoria RAM (ver el apartado anterior).El ciclo de programación no es similar al de escritura de la memoria RAM en cuantoque los requerimientos temporales y de control son totalmente diferentes.

En las referencias de esta capítulo tenemos el modelo AT28C040 del fabricanteAtmel, que es una memoria tipo EEPROM (Electrically Erasable and ProgrammableRead Only Memory). Como puede verse en esta referencia el tiempo de acceso enlectura es de 200 ns mientras que el tiempo de grabación alcanza el valor de 10 ms.Es por esto por lo que no se puede utilizar como memoria RAM de lectura y escritura.

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CY7C1010DV33

2-Mbit (256 K × 8) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-00062 Rev. *E Revised December 2, 2013

2-Mbit (256 K × 8) Static RAM

Features

Pin and function compatible with CY7C1010CV33

High speed

tAA = 10 ns

Low active power

ICC = 90 mA at 10 ns

Low CMOS standby power

ISB2 = 10 mA

2.0 V data retention

Automatic power down when deselected

TTL-compatible inputs and outputs

Easy memory expansion with CE and OE features

Available in Pb-free 36-pin SOJ and 44-pin TSOP II packages

Functional Description

The CY7C1010DV33 is a high performance CMOS Static RAMorganized as 256 K words by 8 bits. Easy memory expansion isprovided by an active LOW Chip Enable (CE), an active LOWOutput Enable (OE), and three-state drivers. Writing to thedevice is accomplished by taking Chip Enable (CE) and WriteEnable (WE) inputs LOW. Data on the eight I/O pins (I/O0through I/O7) is then written into the location specified on theaddress pins (A0 through A17).

Reading from the device is accomplished by taking Chip Enable(CE) and Output Enable (OE) LOW while forcing Write Enable(WE) HIGH. Under these conditions, the contents of the memorylocation specified by the address pins will appear on the I/O pins.

The eight input and output pins (I/O0 through I/O7) are placed ina high impedance state when the device is deselected (CEHIGH), the outputs are disabled (OE HIGH), or during a Writeoperation (CE LOW, and WE LOW).

The CY7C1010DV33 is available in 36-pin SOJ and 44-pinTSOP II packages with center power and ground (revolutionary)pinout.

A0

IO0

IO7

IO1

IO2

IO3

IO4

IO5

IO6

A1A2A3A4A5A6A7A8A9

SE

NS

E A

MP

S

POWER

DOWN

CE

WE

OE

A1

2

A1

3

A1

4

A1

5

A1

6

RO

W D

EC

OD

ER

COLUMN DECODER

256K x 8

ARRAY

INPUT BUFFER

A10

A1

7

A11

Logic Block Diagram

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CY7C1010DV33

Document Number: 001-00062 Rev. *E Page 2 of 16

Contents

Selection Guide ................................................................ 3

Pin Configuration ............................................................. 3

Maximum Ratings ............................................................. 4

Operating Range ............................................................... 4

Electrical Characteristics ................................................. 4

Capacitance ...................................................................... 5

Thermal Resistance .......................................................... 5

AC Test Loads and Waveforms ....................................... 5

Data Retention Characteristics ....................................... 6

Data Retention Waveform ................................................ 6

AC Switching Characteristics ......................................... 7

Switching Waveforms ...................................................... 8

Truth Table ...................................................................... 10

Ordering Information ...................................................... 11

Ordering Code Definitions ......................................... 11

Package Diagrams .......................................................... 12

Acronyms ........................................................................ 14

Document Conventions ................................................. 14

Units of Measure ....................................................... 14

Document History Page ................................................. 15

Sales, Solutions, and Legal Information ...................... 16

Worldwide Sales and Design Support ....................... 16

Products .................................................................... 16

PSoC® Solutions ...................................................... 16

Cypress Developer Community ................................. 16

Technical Support ..................................................... 16

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CY7C1010DV33


Selection Guide

Description -10 Unit

Maximum Access Time 10 ns

Maximum Operating Current 90 mA

Maximum CMOS Standby Current 10 mA

Pin ConfigurationFigure 1. 36-pin SOJ pinout [1] Figure 2. 44-pin TSOP II pinout [1]

1

2

3

4

5

6

7

8

9

11

14

31

32

36

35

34

33

12

13

16

15

29

30

1817 20

19

27

28

25

26

22

21

23

24

NCA4

A3A2

A14

A15 A12NC

NCA13

A5

A6

A7A1

A16

A0

CEIO0

IO1

IO2IO3

WEA17 A10

A9

IO4

IO5

IO6

IO7

OE

A8

VCC

VCC

GNDGND

A11

10

1

2

3

4

5

6

7

8

9

11

14 31

32

36

35

34

33

37

40

39

38

12

13

41

44

43

42

16

15

29

30

NC

1817

2019

27

28

25

26

2221

23

24

NC

NC

NC

NCA4

A3A2

A14

A15 A12

NCNC

NCNC

A13

NC NC

A5

A6

A7A1

A16

A0

CEIO0

IO1

IO2IO3

WEA17 A10

A9

IO4

IO5

IO6

IO7

OE

A8

VCC

VCC

VSS

VSS

A11

10

Note1. NC pins are not connected on the die.

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Maximum Ratings

Exceeding the maximum ratings may impair the useful life of thedevice. These user guidelines are not tested.

Storage Temperature ............................... –65 C to +150 C

Ambient Temperature with Power Applied ......................................... –55 C to +125 C

Supply Voltage on VCC Relative to GND [2] ...............................–0.5 V to +4.6 V

DC Voltage Applied to Outputs in High Z State [2] ................................ –0.3 V to VCC + 0.3 V

DC Input Voltage [2] ............................ –0.3 V to VCC + 0.3 V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage (MIL-STD-883, Method 3015) ................................ > 2001 V

Latch Up Current ................................................... > 200 mA

Operating Range

Range Ambient Temperature VCC

Industrial –40 C to +85 C 3.3V 0.3V

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions-10

UnitMin Max

VOH Output HIGH Voltage VCC = Min; IOH = –4.0 mA 2.4 – V

VOL Output LOW Voltage VCC = Min; IOL = 8.0 mA – 0.4 V

VIH Input HIGH Voltage 2.0 VCC + 0.3 V

VIL Input LOW Voltage[2] –0.3 0.8 V

IIX Input Leakage Current GND < VI < VCC –1 +1 A

IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 A

ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC 100 MHz – 90 mA

83 MHz – 80

66 MHz – 70

40 MHz – 60

ISB1 Automatic CE Power-down Current – TTL Inputs

Max VCC, CE > VIH; VIN > VIH or VIN < VIL, f = fMAX

– 20 mA

ISB2 Automatic CE Power-down Current – CMOS Inputs

Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0

– 10 mA

Note2. VIL (min.) = –2.0V and VIH (max.) = VCC + 2.0V for pulse durations of less than 20 ns.

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Capacitance

Parameter [3] Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit

CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 8 8 pF

COUT I/O capacitance 8 8 pF

Thermal Resistance

Parameter [3] Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit

JA Thermal resistance (junction to ambient)

Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board

59.17 50.66 C/W

JC Thermal resistance (junction to case)

32.63 17.77 C/W

AC Test Loads and WaveformsFigure 3. AC Test Loads and Waveforms [4]

90%

10%

3.0 V

GND

90%

10%

ALL INPUT PULSES

* CAPACITIVE LOAD CONSISTSOF ALL COMPONENTS OF THETEST ENVIRONMENT

Rise Time: 1 V/ns Fall Time: 1 V/ns

30 pF*

OUTPUTZ = 50

50

1.5 V

(b)(a)

3.3 V

OUTPUT

5 pF

(c)

R 317

R2351

High-Z characteristics:

Notes3. Tested initially and after any design or process changes that may affect these parameters.4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 3 (a). High-Z characteristics are tested for all speeds using the test load shown

in Figure 3 (c).

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Data Retention Characteristics


Parameter [5] Description Conditions Min Max Unit

VDR VCC for Data Retention 2 – V

ICCDR Data Retention Current VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V

– 10 mA

tCDR [6] Chip Deselect to Data Retention Time 0 – ns

tR[7] Operation Recovery Time tRC – ns

Data Retention WaveformFigure 4. Data Retention Waveform

3.0V3.0V

tCDR

VDR > 2V

DATA RETENTION MODE

tR

CE

VCC

Notes5. No inputs may exceed VCC + 0.3 V.6. Tested initially and after any design or process changes that may affect these parameters. 7. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.

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AC Switching Characteristics


Parameter [8] Description-10

UnitMin Max

Read Cycle

tpower[9] VCC(typical) to the first access 100 – s

tRC Read Cycle Time 10 – ns

tAA Address to Data Valid – 10 ns

tOHA Data Hold from Address Change 3 – ns

tACE CE LOW to Data Valid – 10 ns

tDOE OE LOW to Data Valid – 5 ns

tLZOE OE LOW to Low Z [10] 0 – ns

tHZOE OE HIGH to High Z[10, 11] – 5 ns

tLZCE CE LOW to Low Z[10] 3 – ns

tHZCE CE HIGH to High Z[10, 11] – 5 ns

tPU CE LOW to Power-up 0 – ns

tPD CE HIGH to Power-down – 10 ns

Write Cycle[12, 13]

tWC Write Cycle Time 10 – ns

tSCE CE LOW to Write End 7 – ns

tAW Address Set-up to Write End 7 – ns

tHA Address Hold from Write End 0 – ns

tSA Address Set-up to Write Start 0 – ns

tPWE WE Pulse Width 7 – ns

tSD Data Set-up to Write End 5 – ns

tHD Data Hold from Write End 0 – ns

tLZWE WE HIGH to Low Z[10] 3 – ns

tHZWE WE LOW to High Z[10, 11] – 5 ns

Notes8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.9. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.11. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 3 on page 5. Transition is measured when the outputs enter a high

impedance state.12. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of

these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.13. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

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Switching WaveformsFigure 5. Read Cycle No. 1 [14, 15]

Figure 6. Read Cycle No. 2 (OE Controlled) [15, 16]

PREVIOUS DATA VALID DATA VALID

RC

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tHZCE

tPD

HIGH

OE

CE

ICC

ISB

IMPEDANCE

ADDRESS

DATA OUT

VCCSUPPLY

CURRENT

Notes14. The device is continuously selected. OE, CE = VIL.15. WE is HIGH for read cycle.16. Address valid before or similar to CE transition LOW.

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Figure 7. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [17, 18]

Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [18]

Switching Waveforms (continued)

tHDtSD

tPWEtSA

tHAtAW

tSCE

tWC

tHZOE

DATAIN VALID

CE

ADDRESS

WE

DATA I/O

OE

NOTE 19

DATA VALID

tHDtSD

tLZWE

tPWEtSA

tHAtAW

tSCE

tWC

tHZWE

CE

ADDRESS

WE

DATA I/O NOTE 19

Notes17. Data IO is high impedance if OE = VIH.18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.19. During this period, the I/Os are in output state and input signals should not be applied.

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Truth Table

CE OE WE I/O0–I/O7 I/O8–I/O15 Mode Power

H X X High Z High Z Power Down Standby (ISB)

L L H Data Out Data Out Read All Bits Active (ICC)

L X L Data In Data In Write All Bits Active (ICC)

L H H High Z High Z Selected, Outputs Disabled Active (ICC)

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Features• Read Access Time – 200 ns

• Automatic Page Write Operation

– Internal Address and Data Latches for 256 Bytes

– Internal Control Timer

• Fast Write Cycle Time

– Page Write Cycle Time – 10 ms Maximum

– 1 to 256 Byte Page Write Operation

• Low Power Dissipation

– 50 mA Active Current

• Hardware and Software Data Protection

• DATA Polling for End of Write Detection

• High Reliability CMOS Technology

– Endurance: 10,000 Cycles

– Data Retention: 10 Years

• Single 5V 10% Supply

• CMOS and TTL Compatible Inputs and Outputs

• JEDEC Approved Byte-Wide Pinout

1. DescriptionThe AT28C040 is a high-performance electrically erasable and programmable read-

only memory (EEPROM). Its 4 megabits of memory is organized as 524,288 words by

8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device

offers access times to 200 ns with power dissipation of just 440 mW.

The AT28C040 is accessed like a static RAM for the read or write cycle without the

need for external components. The device contains a 256-byte page register to allow

writing of up to 256 bytes simultaneously. During a write cycle, the address and 1 to

256 bytes of data are internally latched, freeing the address and data bus for other

operations. Following the initiation of a write cycle, the device will automatically write

the latched data using an internal control timer. The end of a write cycle can be

detected by Data Polling of I/O7. Once the end of a write cycle has been detected, a

new access for a read or write can begin.

Atmel's AT28C040 has additional features to ensure high quality and manufacturabil-

ity. The device utilizes internal error correction for extended endurance and improved

data retention characteristics. An optional software data protection mechanism is

available to guard against inadvertent writes. The device also includes an extra 256

bytes of EEPROM for device identification or tracking.

4-Megabit

(512K x 8)

Paged Parallel

EEPROMs

AT28C040

0542F–PEEPR–2/09

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0542F–PEEPR–2/09

AT28C040

2. Pin Configurations

2.1 44-lead LCC – Top View

Pin Name Function

A0 - A18 Addresses

CE Chip Enable

OE Output Enable

WE Write Enable

I/O0 - I/O7 Data Inputs/Outputs

NC No Connect

7

8

9

10

11

12

13

14

15

16

17

39

38

37

36

35

34

33

32

31

30

29

A12

A7

A6

A5

NC

NC

NC

A4

A3

A2

A1

A13

A8

A9

A11

NC

NC

NC

NC

OE

A10

CE

6 5 4 3 2 1

44

43

42

41

40

18

19

20

21

22

23

24

25

26

27

28

A0

I/O

0

I/O

1

I/O

2

VS

S

NC

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

A15

A16

A18

NC

NC

NC

VC

C

WE

NC

A17

A14

2.2 32-lead Flatpack – Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

A18

A16

A15

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O0

I/O1

I/O2

GND

VCC

WE

A17

A14

A13

A8

A9

A11

OE

A10

CE

I/O7

I/O6

I/O5

I/O4

I/O3

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0542F–PEEPR–2/09

AT28C040

3. Block Diagram

4. Absolute Maximum Ratings*

Temperature Under Bias................................ -55 C to +125 C *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature ..................................... -65 C to +150 C

All Input Voltages

(including NC pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to VCC + 0.6V

Voltage on OE and A9

with Respect to Ground ...................................-0.6V to +13.5V

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AT28C040

5. Device Operation

5.1 ReadThe AT28C040 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their systems.

5.2 Byte WriteA low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automati-cally time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.

5.3 Page WriteThe page write operation of the AT28C040 allows 1 to 256 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 255 additional bytes. Each successive byte must be written within 150 s (tBLC) of the previous byte. If the tBLC

limit is exceeded, the AT28C040 will cease accepting data and commence the internal program-ming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A8 - A18 inputs. For each WE high to low transition during the page write operation, A8 - A18 must be the same.

The A0 to A7 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are spec-ified for writing will be written; unnecessary cycling of other bytes within the page does not occur.

5.4 Data PollingThe AT28C040 features Data Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. Data Polling may begin at anytime during the write cycle.

5.5 Toggle BitIn addition to Data Polling, the AT28C040 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop tog-gling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.

5.6 Data ProtectionIf precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel® has incorporated both hardware and software features that will protect the memory against inadvertent writes.

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AT28C040

5.6.1 Hardware Protection

Hardware features protect against inadvertent writes to the AT28C040 in the following ways: (a) VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay – once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.

5.6.2 Software Data Protection

A software controlled data protection feature has been implemented on the AT28C040. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C040 is shipped from Atmel with SDP disabled.

SDP is enabled when the host system issues a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algo-rithm). After writing the 3-byte command sequence and after tWC, the entire AT28C040 will be protected against inadvertent write operations. It should be noted that once protected, the host can still perform a byte or page write to the AT28C040. To do so, the same 3-byte command sequence used to enable SDP must precede the data to be written.

Once set, SDP will remain active unless the disable command sequence is issued. Power transi-tions do not disable SDP, and SDP will protect the AT28C040 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device, and the memory addresses used in the sequence may be written with data in either a byte or page write operation.

After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations.

5.7 Device IdentificationAn extra 256 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V 0.5V and using address locations 7FF80H to 7FFFFH, the bytes may be writ-ten to or read from in the same manner as the regular memory array.

5.8 Optional Chip Erase ModeThe entire device can be erased using a 6-byte software erase code. Please see Software Chip Erase application note for details.El

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0542F–PEEPR–2/09

AT28C040

Notes: 1. X can be VIL or VIH.

2. Refer to AC Programming Waveforms.

6. DC and AC Operating Range

AT28C040-20 Operation

Read Program

Operating Temperature (Case)Industrial -40°C - 85°C -40°C - 85°C

Extended -55°C - 125°C -40°C - 85°C

VCC Power Supply 5V 10% 5V 10%

7. Operating Modes

Mode CE OE WE I/O

Read VIL VIL VIH DOUT

Write(2) VIL VIH VIL DIN

Write Inhibit X X VIH

Write Inhibit X VIL X

Output Disable X VIH X High Z

8. DC Characteristics

Symbol Parameter Condition Min Max Units

ILI Input Load Current VIN = 0V to VCC + 1V 10 µA

ILO Output Leakage Current VI/O = 0V to VCC 10 µA

ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA

VIL Input Low Voltage 0.8 V

VIH Input High Voltage 2.0 V

VOL Output Low Voltage IOL = 2.1 mA 0.45 V

VOH1 Output High Voltage IOH = -400 µA 2.4 V

VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 VElec

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AT28C040

10. AC Read Waveforms(1)(2)(3)(4)

Notes: 1. CE May be delayed up to tACC - tCE after the address transition without impact on tACC.

2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change

without impact on tACC.

3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

11. Input Test Waveforms and Measurement Level

tR, tF < 5 ns

12. Output Test Load

Note: 1. This parameter is characterized and is not 100% tested.

9. AC Read Characteristics

Symbol Parameter

AT28C040-20

UnitsMin Max

tACC Address to Output Delay 200 ns

tCE(1) CE to Output Delay 200 ns

tOE(2) OE to Output Delay 0 55 ns

tDF(3)(4) CE or OE to Output Float 0 55 ns

tOH Output Hold from OE, CE or Address, whichever occurred first 0 ns

13. Pin Capacitancef = 1 MHz, T = 25°C(1)

Symbol Typ Max Units Conditions

CIN 4 10 pF VIN = 0V

COUT 8 12 pF VOUT = 0V

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AT28C040

15. AC Write Waveforms

15.1 WE Controlled

15.2 CE Controlled

14. AC Write Characteristics

Symbol Parameter Min Max Units

tAS, tOES Address, OE Set-up Time 0 ns

tAH Address Hold Time 50 ns

tCS Chip Select Set-up Time 0 ns

tCH Chip Select Hold Time 0 ns

tWP Write Pulse Width (WE or CE) 100 ns

tDS Data Set-up Time 50 ns

tDH, tOEH Data, OE Hold Time 0 ns

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17. Page Mode Write Waveforms(1)(2)

Notes: 1. A8 through A18 must specify the page address during each high to low transition of WE (or CE).

2. OE must be high only when WE and CE are both low.

16. Page Mode Characteristics

Symbol Parameter Min Max Units

tWC Write Cycle Time 10 ms

tAS Address Set-up Time 0 ns

tAH Address Hold Time 50 ns

tDS Data Set-up Time 50 ns

tDH Data Hold Time 0 ns

tWP Write Pulse Width 100 ns

tBLC Byte Load Cycle Time 150 s

tWPH Write Pulse Width High 50 ns

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AT28C040

18. Software Data

Protection Enable Algorithm(1)

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. Write Protect state will be activated at end of write

even if no other data is loaded.

3. Write Protect state will be deactivated at end of write

period even if no other data is loaded.

4. 1 to 256 bytes of data are loaded.

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA A0

TO

ADDRESS 5555

LOAD DATA XX

TO

ANY ADDRESS(4)

LOAD LAST BYTE

TO

LAST ADDRESSENTER DATA

PROTECT STATE

WRITES ENABLED(2)

19. Software Data

Protection Disable Algorithm(1)

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 55

TO

ADDRESS 2AAA

LOAD DATA 80

TO

ADDRESS 5555

LOAD DATA AA

TO

ADDRESS 5555

LOAD DATA 20

TO

ADDRESS 5555

LOAD DATA XX

TO

ANY ADDRESS(4)

LOAD LAST BYTE

TO

LAST ADDRESS

LOAD DATA 55

TO

ADDRESS 2AAA

EXIT DATA

PROTECT STATE(3)

20. Software Protected Program Cycle Waveform(1)(2)(3)

Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above.

2. After the command sequence has been issued and a page write operation follows, the page address inputs (A8 - A18) must

be the same for each high to low transition of WE (or CE).

3. OE must be high only when WE and CE are both low.

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Notes: 1. These parameters are characterized and not 100% tested.

2. See AC Read Characteristics.

22. Data Polling Waveforms

Notes: 1. These parameters are characterized and not 100% tested.

2. See AC Read Characteristics.

24. Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

21. Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units


tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tWR Write Recovery Time 0 ns

23. Toggle Bit Characteristics(1)

Symbol Parameter Min Typ Max Units


tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tOEHP OE High Pulse 150 ns

tWR Write Recovery Time 0 nsElec

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V1.0 7.1

7.- Dispositivos Periféricos

7.1.- Introducción . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2

7.2.- Clasificación . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3

7.3.- Interfaz paralelo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3

7.4.- Interfaz serie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3

7.5.- Controlador de tiempo y frecuencia . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4

7.6.- Controlador de interrupciones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4

7.7.- Controlador de ADM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5

7.9.- Puerto analógico . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5

7.10.- Otros dispositivos periféricos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5

7.11.- Referencias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7

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7.1.- Introducción

Los dispositivos periféricos son elementos complejos programablescomplementarios a una UCP. De una forma genérica podemos decir que todos loselementos que no es UCP ni UCM es un dispositivo periférico (a la UCP).

Los dispositivos periféricos sirven para realizar funciones por medio de circuiteríamás eficientemente que si se realizaran por medio de programación de la UCP. Esdecir que los dispositivos periféricos permiten que la UCP se descargue de tareasfácilmente realizable por estos dispositivos, así ella puede dedicarse a controlar todoel sistema. Los dispositivos periféricos son trabajadores especializados en unadeterminada tarea. Son programables para establecerles el método de trabajo dentrode su especialidad y se comunican con la UCP por medio de los buses del sistema(direcciones, datos y control).

En todos los dispositivos periféricos podemos encontrar tres tipos de registros queson los que utiliza el programador del sistema (a través de la UCP) para manejar ysupervisar su funcionamiento. Lo mas frecuente es organizarlo en los tres tipossiguientes:

1. Registros de programación, que sirven para establecer la forma defuncionamiento del dispositivo.

2. Registros de control, que sirven para obtener información del estado deldispositivo y lo que está haciendo, así como para enviarle órdenes para suejecución.

3. Registros de datos, por medio de los cuales el dispositivo transfiereinformación a o desde la UCP.

Dependiendo del tipo de dispositivo periférico, veremos que el número deregistros de cada tipo varía según sea necesario.

Lo más frecuente es que estos registros sean de 8 bits y en muchos casos los deprogramación y los de control se programan bit a bit. Esto significa que aunque unregistro dispone de 8 bits, cada uno de los bits sirve para activar o desactivar unafunción dentro del dispositivo. También nos encontraremos con grupos de 2 o mas bitspara seleccionar determinadas funciones. Todo esto nos lo dice el fabricante deldispositivo en su manual.

La utilización de estos dispositivos se hace mayoritariamente por programación(en muy pocos casos pueden ser controlados manualmente). El programa que ejecutala UCP (y que es escrito por nosotros) va realizando operaciones de escritura y delectura para configurar y hacer funcionar los dispositivos como se desee dentro de lasposibilidades que tiene cada uno de ellos. Para lograr esto hay que conocer cómofunciona cada dispositivo y cómo se ha de manejar.

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7.2.- Clasificación

En el mercado nos encontramos con una enorme variedad de dispositivosperiféricos. Nosotros los vamos a clasificar en las cuatro siguientes categorías:

1. Interfaz paralelo . Es un clásico para poder gobernar dispositivos digitalesbit a bit o por byte. Tiene propiedades importantes como alta velocidad detransferencia (B/s) pero tiene el inconveniente de su poco alcance (unosmetros en el mejor caso).

2. Interfaz serie . Su uso está muy extendido (USB, FireWire, CAN, I2C, ...) yaque simplifica enormemente el conexionado y, además, tiene un granalcance.

3. Expansión de funciones . En esta categoría nos encontramos con muchoselementos de los que solo citaremos algunas: Controlador de tiempo yfrecuencia, controlador de interrupciones y controlador de ADM (AccesoDirecto a Memoria)

4. Puerto analógico . Esta categoría es extremadamente útil cuando se trabajacon señales analógicas con tratamiento digital (Mixed signal) y suele estarincorporada en la mayoría de los microcontroladores actuales.

7.3.- Interfaz paralelo

El interfaz paralelo o puerto paralelo, está descrito en detalle en el capítulo 8 dellibro “Sistemas Basados en Microprocesadores” en los apartados 8.1 a 8.4 y 8.5. Poreso, en este documento solamente hacemos la inclusión de la referencia técnica delfabricante en la referencia 8255, que también describe su funcionamiento.

Por otro lado, el :C MSP430 dispone de una interfaz paralelo ligeramentediferente. Para ver este caso hay que consultar los documentos externos“MSP430G2553 Hojas de datos” y “MSP430x2xx Family Users Guide” disponibles enel Aula Virtual. En el primero encontramos las características eléctricas y temporalesde funcionamiento mientras que en el segundo hay una descripción muy completa deesta interfaz que en este caso la denominan “Digital I/O” y es el capítulo 8 de estedocumento.

7.4.- Interfaz serie

De forma similar al caso anterior, el controlador de la interfaz serie o puerto serie,se encuentra descrito detalladamente en el capítulo 8 del libro “Sistemas Basados enMicroprocesadores” en los apartados 8.1 a 8.4 y 8.5. Por eso, en este documento

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solamente hacemos la inclusión de la referencia técnica del fabricante en la referencia82050, que también describe su funcionamiento.

En el caso del MSP430, el puerto serie se denomina “USI” (Universal SerialInterface) y la tenemos en los documentos externos “MSP430G2553 Hojas de datos”y “MSP430x2xx Family Users Guide” disponibles en el Aula Virtual. En el primeroencontramos las características eléctricas y temporales de funcionamiento mientrasque en el segundo hay una descripción muy completa de esta interfaz en los capítulos14 a 19 de este documento.

7.5.- Controlador de tiempo y frecuencia

De nuevo, como en el apartado anterior, el controlador de tiempo y frecuencia otemporizador, se encuentra descrito detalladamente en el capítulo 8 del libro “SistemasBasados en Microprocesadores” en los apartados 8.1 a 8.4 y 8.6. Por eso, en estedocumento solamente hacemos la inclusión de la referencia técnica del fabricante enla referencia 8254, que también describe su funcionamiento.

En el caso del MSP430, el temporizador se denomina “Timer” y lo tenemos en losdocumentos externos “MSP430G2553 Hojas de datos” y “MSP430x2xx Family UsersGuide” disponibles en el Aula Virtual. En el primero encontramos las característicaseléctricas y temporales de funcionamiento mientras que en el segundo hay unadescripción muy completa de esta interfaz en los capítulos 12 y 13 de este documento.

7.6.- Controlador de interrupciones

Como en los casos anteriores, el controlador de interrupciones se encuentradescrito detalladamente en el capítulo 7 del libro “Sistemas Basados enMicroprocesadores” en los apartados 7.1 y 7.2. Por eso, en este documento solamentehacemos la inclusión de la referencia técnica del fabricante en la referencia 8259, quetambién describe su funcionamiento.

En el caso del MSP430, el funcionamiento del control de interrupciones lotenemos en los documentos externos “MSP430G2553 Hojas de datos” y “MSP430x2xxFamily Users Guide” disponibles en el Aula Virtual. En el primero encontramos lascaracterísticas eléctricas y temporales de funcionamiento mientras que en el segundohay una descripción muy completa de este controlador en el capítulo 2 de estedocumento.

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7.7.- Controlador de ADM

Como en los casos anteriores, el controlador de ADM se encuentra descritodetalladamente en el capítulo 7 del libro “Sistemas Basados en Microprocesadores” enlos apartados 7.1 y 7.3. Por eso, en este documento solamente hacemos la inclusiónde la referencia técnica del fabricante en la referencia 8237, que también describe sufuncionamiento.

En el caso del MSP430, algunos modelos incluyen un controlador de ADM quelo podemos ver en el capítulo 6 del documento externo “MSP430x2xx Family UsersGuide” disponible en el Aula Virtual.

7.9.- Puerto analógico

En este caso nos encontramos con dos posibilidades, que el puerto analógico seade entrada (datos hacia la UCP) o de salida.

• Entrada analógica . Es el caso más frecuente de encontrar en losmicrocontroladores. En nuestro caso y dado que utilizamos el MSP4390 deTexas Instruments, disponemos de una entrada analógica de 10 bitscompartida entre varios canales de entrada.

En el caso del MSP430, la entrada analógica se denomina “ADC10” (10-bitAnalog to Digital Converter) y la tenemos en los documentos externos“MSP430G2553 Hojas de datos” y “MSP430x2xx Family Users Guide”disponibles en el Aula Virtual. En el primero encontramos las característicaseléctricas y temporales de funcionamiento mientras que en el segundo hay unadescripción muy completa de este puerto en el capítulo 22 de este documento.

• Salida analógica . Cada día es más frecuente encontrar SBM con salidaanalógica, sin embargo no es demasiado frecuente encontrar :C que la tenga.

En el caso del MSP430, hay modelos que disponen de ete puerto analógicode salida y se denomina “DCA12" y lo tenemos en el capítulo 25 deldocumento “MSP430x2xx Family Users Guide” disponibles en el Aula Virtual.

7.10.- Otros dispositivos periféricos

Los dispositivos periféricos o controladores citados en los apartados anterioresson los que utilizamos en SED, pero como se dijo en el apartado 7.1 existen muchosmás que son prácticamente imposible de describir. Se han elegido éstos por ser losmas simples de entender y se usan muy frecuentemente.

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En el caso de la familia de :C MSP430 tenemos los siguientes dispositivosademás de los citados (solo a modo de cita):

• Basic Clock Module+

• Flash Memory Controller

• Supply Voltage Supervisor (SVS)

• Watchdog Timer+ (WDT+)

• Hardware Multiplier

• Universal Serial Communication Interface, SPI

• Universal Serial Communication Interface, I2C

• TLV (Tag-Length-Value)

• SD16_A (16-bit sigma-delta analog-to-digital conver sion module)

• ADC12

• SD24_A (24-bit sigma-delta analog-to-digital conver ter)

• Embedded Emulation Module (EEM)

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7.11.- ReferenciasEl

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September 1993 Order Number: 231164-005

8254PROGRAMMABLE INTERVAL TIMER

Y Compatible with All Intel and MostOther Microprocessors

Y Handles Inputs from DC to 10 MHzÐ 8 MHz 8254Ð 10 MHz 8254-2

Y Status Read-Back Command

Y Six Programmable Counter Modes

Y Three Independent 16-Bit Counters

Y Binary or BCD Counting

Y Single a5V Supply

Y Available in EXPRESSÐ Standard Temperature Range

The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcom-puter system design. It provides three independent 16-bit counters, each capable of handling clock inputs upto 10 MHz. All modes are software programmable. The 8254 is a superset of the 8253.

The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.

231164–1

Figure 1. 8254 Block Diagram

231164–2

Figure 2. Pin Configuration

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Table 1. Pin Description

SymbolPin

Type Name and FunctionNo.

D7–D0 1–8 I/O DATA: Bi-directional three state data bus lines, connected to systemdata bus.

CLK 0 9 I CLOCK 0: Clock input of Counter 0.

OUT 0 10 O OUTPUT 0: Output of Counter 0.

GATE 0 11 I GATE 0: Gate input of Counter 0.

GND 12 GROUND: Power supply connection.

VCC 24 POWER: a5V power supply connection.

WR 23 I WRITE CONTROL: This input is low during CPU write operations.

RD 22 I READ CONTROL: This input is low during CPU read operations.

CS 21 I CHIP SELECT: A low on this input enables the 8254 to respond toRD and WR signals. RD and WR are ignored otherwise.

A1, A0 20–19 I ADDRESS: Used to select one of the three Counters or the ControlWord Register for read or write operations. Normally connected tothe system address bus.

A1 A0 Selects

0 0 Counter 00 1 Counter 11 0 Counter 21 1 Control Word Register


OUT 2 17 O OUT 2: Output of Counter 2.




OUT 1 13 O OUT 1: Output of Counter 1.

FUNCTIONAL DESCRIPTION

General

The 8254 is a programmable interval timer/counterdesigned for use with Intel microcomputer systems.It is a general purpose, multi-timing element that canbe treated as an array of I/O ports in the systemsoftware.

The 8254 solves one of the most common problemsin any microcomputer system, the generation of ac-curate time delays under software control. Instead ofsetting up timing loops in software, the programmerconfigures the 8254 to match his requirements andprograms one of the counters for the desired delay.After the desired delay, the 8254 will interrupt theCPU. Software overhead is minimal and variablelength delays can easily be accommodated.

Some of the other counter/timer functions commonto microcomputers which can be implemented withthe 8254 are:

# Real time clock

# Event-counter

# Digital one-shot

# Programmable rate generator

# Square wave generator

# Binary rate multiplier

# Complex waveform generator

# Complex motor controller

Block Diagram

DATA BUS BUFFER

This 3-state, bi-directional, 8-bit buffer is used to in-terface the 8254 to the system bus (see Figure 3).

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231164–3

Figure 3. Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions

READ/WRITE LOGIC

The Read/Write Logic accepts inputs from the sys-tem bus and generates control signals for the otherfunctional blocks of the 8254. A1 and A0 select oneof the three counters or the Control Word Registerto be read from/written into. A ‘‘low’’ on the RD in-put tells the 8254 that the CPU is reading one of thecounters. A ‘‘low’’ on the WR input tells the 8254that the CPU is writing either a Control Word or aninitial count. Both RD and WR are qualified by CS;RD and WR are ignored unless the 8254 has beenselected by holding CS low.

CONTROL WORD REGISTER

The Control Word Register (see Figure 4) is selectedby the Read/Write Logic when A1,A0 e 11. If theCPU then does a write operation to the 8254, thedata is stored in the Control Word Register and isinterpreted as a Control Word used to define theoperation of the Counters.

The Control Word Register can only be written to;status information is available with the Read-BackCommand.

COUNTER 0, COUNTER 1, COUNTER 2

These three functional blocks are identical in opera-tion, so only a single Counter will be described. Theinternal block diagram of a single counter is shownin Figure 5.

The Counters are fully independent. Each Countermay operate in a different Mode.

The Control Word Register is shown in the figure; itis not part of the Counter itself, but its contents de-termine how the Counter operates.

The status register, shown in Figure 5, whenlatched, contains the current contents of the ControlWord Register and status of the output and nullcount flag. (See detailed explanation of the Read-Back command.)

The actual counter is labelled CE (for ‘‘Counting Ele-ment’’). It is a 16-bit presettable synchronous downcounter.

OLM and OLL are two 8-bit latches. OL stands for‘‘Output Latch’’; the subscripts M and L stand for‘‘Most significant byte’’ and ‘‘Least significant byte’’

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231164–4

Figure 4. Block Diagram Showing Control Word Register and Counter Functions

231164–5

Figure 5. Internal Block Diagram of a Counter

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respectively. Both are normally referred to as oneunit and called just OL. These latches normally ‘‘fol-low’’ the CE, but if a suitable Counter Latch Com-mand is sent to the 8254, the latches ‘‘latch’’ thepresent count until read by the CPU and then returnto ‘‘following’’ the CE. One latch at a time is enabledby the counter’s Control Logic to drive the internalbus. This is how the 16-bit Counter communicatesover the 8-bit internal bus. Note that the CE itselfcannot be read; whenever you read the count, it isthe OL that is being read.

Similarly, there are two 8-bit registers called CRMand CRL (for ‘‘Count Register’’). Both are normallyreferred to as one unit and called just CR. When anew count is written to the Counter, the count isstored in the CR and later transferred to the CE. TheControl Logic allows one register at a time to beloaded from the internal bus. Both bytes are trans-ferred to the CE simultaneously. CRM and CRL arecleared when the Counter is programmed. In thisway, if the Counter has been programmed for onebyte counts (either most significant byte only or leastsignificant byte only) the other byte will be zero.Note that the CE cannot be written into; whenever acount is written, it is written into the CR.

The Control Logic is also shown in the diagram.CLK n, GATE n, and OUT n are all connected to theoutside world through the Control Logic.

8254 SYSTEM INTERFACE

The 8254 is a component of the Intel MicrocomputerSystems and interfaces in the same manner as all

other peripherals of the family. It is treated by thesystem’s software as an array of peripheral I/Oports; three are counters and the fourth is a controlregister for MODE programming.

Basically, the select inputs A0,A1 connect to the A0,A1 address bus signals of the CPU. The CS can bederived directly from the address bus using a linearselect method. Or it can be connected to the outputof a decoder, such as an Intel 8205 for larger sys-tems.

OPERATIONAL DESCRIPTION

General

After power-up, the state of the 8254 is undefined.The Mode, count value, and output of all Countersare undefined.

How each Counter operates is determined when it isprogrammed. Each Counter must be programmedbefore it can be used. Unused counters need not beprogrammed.

Programming the 8254

Counters are programmed by writing a Control Wordand then an initial count.

The Control Words are written into the Control WordRegister, which is selected when A1,A0 e 11. TheControl Word itself specifies which Counter is beingprogrammed.

231164–6

Figure 6. 8254 System Interface

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Control Word FormatA1,A0 e 11 CS e 0 RD e 1 WR e 0

D7 D6 D5 D4 D3 D2 D1 D0

SC1 SC0 RW1 RW0 M2 M1 M0 BCD

SCÐSelect Counter

SC1 SC0

0 0 Select Counter 0



1 1 Read-Back Command

(see Read Operations)

RWÐRead/Write

RW1 RW0

0 0 Counter Latch Command (see Read

Operations)

0 1 Read/Write least significant byte only

1 0 Read/Write most significant byte only

1 1 Read/Write least significant byte first,

then most significant byte

MÐMode

M2 M1 M0

0 0 0 Mode 0

0 0 1 Mode 1

X 1 0 Mode 2

X 1 1 Mode 3

1 0 0 Mode 4

1 0 1 Mode 5

BCD

0 Binary Counter 16-bits

1 Binary Coded Decimal (BCD) Counter

(4 Decades)

NOTE:Don’t care bits (X) should be 0 to insure compatibility with future Intel products.

Figure 7. Control Word Format

By contrast, initial counts are written into the Coun-ters, not the Control Word Register. The A1,A0 in-puts are used to select the Counter to be writteninto. The format of the initial count is determined bythe Control Word used.

Write Operations

The programming procedure for the 8254 is veryflexible. Only two conventions need to be remem-bered:

1) For each Counter, the Control Word must be writ-ten before the initial count is written.

2) The initial count must follow the count formatspecified in the Control Word (least significantbyte only, most significant byte only, or least sig-nificant byte and then most significant byte).

Since the Control Word Register and the threeCounters have separate addresses (selected by theA1,A0 inputs), and each Control Word specifies theCounter it applies to (SC0,SC1 bits), no special in-struction sequence is required. Any programmingsequence that follows the conventions in Figure 7 isacceptable.

A new initial count may be written to a Counter atany time without affecting the Counter’s pro-grammed Mode in any way. Counting will be affectedas described in the Mode definitions. The new countmust follow the programmed count format.

If a Counter is programmed to read/write two-bytecounts, the following precaution applies: A programmust not transfer control between writing the firstand second byte to another routine which also writesinto that same Counter. Otherwise, the Counter willbe loaded with an incorrect count.

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A1 A0

Control WordÐCounter 0 1 1

LSB of countÐCounter 0 0 0

MSB of countÐCounter 0 0 0







A1 A0










A1 A0










A1 A0










NOTE:In all four examples, all Counters are programmed to read/write two-byte counts. These are only four of many possibleprogramming sequences.

Figure 8. A Few Possible Programming Sequences

Read Operations

It is often desirable to read the value of a Counterwithout disturbing the count in progress. This is easi-ly done in the 8254.

There are three possible methods for reading thecounters: a simple read operation, the CounterLatch Command, and the Read-Back Command.Each is explained below. The first method is to per-form a simple read operation. To read the Counter,which is selected with the A1, A0 inputs, the CLKinput of the selected Counter must be inhibited byusing either the GATE input or external logic. Other-wise, the count may be in the process of changingwhen it is read, giving an undefined result.

COUNTER LATCH COMMAND

The second method uses the ‘‘Counter Latch Com-mand’’. Like a Control Word, this command is writtento the Control Word Register, which is selectedwhen A1,A0 e 11. Also like a Control Word, theSC0, SC1 bits select one of the three Counters, buttwo other bits, D5 and D4, distinguish this commandfrom a Control Word.

A1,A0 e 11; CS e 0; RD e 1; WR e 0

D7 D6 D5 D4 D3 D2 D1 D0

SC1 SC0 0 0 X X X X

SC1,SC0Ðspecify counter to be latched

SC1 SC0 Counter

0 0 0

0 1 1

1 0 2

1 1 Read-Back Command

D5,D4Ð00 designates Counter Latch Command

XÐdon’t care

NOTE:Don’t care bits (X) should be 0 to insure compatibilitywith future Intel products.

Figure 9. Counter Latching Command Format

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The selected Counter’s output latch (OL) latches thecount at the time the Counter Latch Command isreceived. This count is held in the latch until it is readby the CPU (or until the Counter is reprogrammed).The count is then unlatched automatically and theOL returns to ‘‘following’’ the counting element (CE).This allows reading the contents of the Counters‘‘on the fly’’ without affecting counting in progress.Multiple Counter Latch Commands may be used tolatch more than one Counter. Each latched Coun-ter’s OL holds its count until it is read. Counter LatchCommands do not affect the programmed Mode ofthe Counter in any way.

If a Counter is latched and then, some time later,latched again before the count is read, the secondCounter Latch Command is ignored. The count readwill be the count at the time the first Counter LatchCommand was issued.

With either method, the count must be read accord-ing to the programmed format; specifically, if theCounter is programmed for two byte counts, twobytes must be read. The two bytes do not have to beread one right after the other; read or write or pro-gramming operations of other Counters may be in-serted between them.

Another feature of the 8254 is that reads and writesof the same Counter may be interleaved; for exam-ple, if the Counter is programmed for two bytecounts, the following sequence is valid.

1) Read least significant byte.

2) Write new least significant byte.

3) Read most significant byte.

4) Write new most significant byte.

If a Counter is programmed to read/write two-bytecounts, the following precaution applies: A programmust not transfer control between reading the firstand second byte to another routine which also readsfrom that same Counter. Otherwise, an incorrectcount will be read.

READ-BACK COMMAND

The third method uses the Read-Back Command.This command allows the user to check the countvalue, programmed Mode, and current states of theOUT pin and Null Count flag of the selected coun-ter(s).

The command is written into the Control Word Reg-ister and has the format shown in Figure 10. Thecommand applies to the counters selected by set-ting their corresponding bits D3, D2, D1 e 1.

A0, A1 e 11 CS e 0 RD e 1 WR e 0

D7 D6 D5 D4 D3 D2 D1 D0

1 1 COUNT STATUS CNT 2 CNT 1 CNT 0 0

D5: 0 e Latch count of selected counter(s)D4: 0 e Latch status of selected counters(s)D3: 1 e Select Counter 2D2: 1 e Select Counter 1D1: 1 e Select Counter 0D0: Reserved for future expansion; Must be 0

Figure 10. Read-Back Command Format

The read-back command may be used to latch multi-ple counter output latches (OL) by setting theCOUNT bit D5 e 0 and selecting the desired coun-ter(s). This single command is functionally equiva-lent to several counter latch commands, one foreach counter latched. Each counter’s latched countis held until it is read (or the counter is repro-grammed). The counter is automatically unlatchedwhen read, but other counters remain latched untilthey are read. If multiple count read-back commandsare issued to the same counter without reading thecount, all but the first are ignored; i.e., the countwhich will be read is the count at the time the firstread-back command was issued.

The read-back command may also be used to latchstatus information of selected counter(s) by settingSTATUS bit D4 e 0. Status must be latched to beread; status of a counter is accessed by a read fromthat counter.

The counter status format is shown in Figure 11. BitsD5 through D0 contain the counter’s programmedMode exactly as written in the last Mode ControlWord. OUTPUT bit D7 contains the current state ofthe OUT pin. This allows the user to monitor thecounter’s output via software, possibly eliminatingsome hardware from a system.

D7 D6 D5 D4 D3 D2 D1 D0

OutputNull

RW1 RW0 M2 M1 M0 BCDCount

D7 1 e OUT Pin is 10 e OUT Pin is 0

D6 1 e Null Count0 e Count available for reading

D5–D0 Counter programmed mode (see Figure7)

Figure 11. Status Byte

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NULL COUNT bit D6 indicates when the last countwritten to the counter register (CR) has been loadedinto the counting element (CE). The exact time thishappens depends on the Mode of the counter and isdescribed in the Mode Definitions, but until the countis loaded into the counting element (CE), it can’t beread from the counter. If the count is latched or readbefore this time, the count value will not reflect thenew count just written. The operation of Null Countis shown in Figure 12.

This Action Causes

A. Write to the control word register;(1) Null Count e 1

B. Write to the count register (CR);(2) Null Count e 1

C. New Count is loaded into Null Count e 0

CE (CRxCE);

NOTE:1. Only the counter specified by the control word willhave its Null Count set to 1. Null count bits of othercounters are unaffected.2. If the counter is programmed for two-byte counts(least significant byte then most significant byte) NullCount goes to 1 when the second byte is written.

Figure 12. Null Count Operation

If multiple status latch operations of the counter(s)are performed without reading the status, all but thefirst are ignored; i.e., the status that will be read isthe status of the counter at the time the first statusread-back command was issued.

Both count and status of the selected counter(s)may be latched simultaneously by setting both

COUNT and STATUS bits D5,D4 e 0. This is func-tionally the same as issuing two separate read-backcommands at once, and the above discussions ap-ply here also. Specifically, if multiple count and/orstatus read-back commands are issued to the samecounter(s) without any intervening reads, all but thefirst are ignored. This is illustrated in Figure 13.

If both count and status of a counter are latched, thefirst read operation of that counter will return latchedstatus, regardless of which was latched first. Thenext one or two reads (depending on whether thecounter is programmed for one or two type counts)return latched count. Subsequent reads return un-latched count.

CS RD WR A1 A0

0 1 0 0 0 Write into Counter 0



0 1 0 1 1 Write Control Word

0 0 1 0 0 Read from Counter 0



0 0 1 1 1 No-Operation (3-State)

1 X X X X No-Operation (3-State)

0 1 1 X X No-Operation (3-State)

Figure 14. Read/Write Operations Summary

CommandDescription Result

D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 0 0 0 1 0 Read back count and status of Count and status latched

Counter 0 for Counter 0

1 1 1 0 0 1 0 0 Read back status of Counter 1 Status latched for Counter 1

1 1 1 0 1 1 0 0 Read back status of Counters 2, 1 Status latched for Counter

2, but not Counter 1

1 1 0 1 1 0 0 0 Read back count of Counter 2 Count latched for Counter 2

1 1 0 0 0 1 0 0 Read back count and status of Count latched for Counter 1,

Counter 1 but not status

1 1 1 0 0 0 1 0 Read back status of Counter 1 Command ignored, status

already latched for Counter 1

Figure 13. Read-Back Command Example

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Mode Definitions

The following are defined for use in describing theoperation of the 8254.

CLK Pulse: a rising edge, then a falling edge, inthat order, of a Counter’s CLK in-put.

Trigger: a rising edge of a Counter’s GATEinput.

Counter loading: the transfer of a count from the CRto the CE (refer to the ‘‘FunctionalDescription’’)

MODE 0: INTERRUPT ON TERMINAL COUNT

Mode 0 is typically used for event counting. After theControl Word is written, OUT is initially low, and willremain low until the Counter reaches zero. OUT thengoes high and remains high until a new count or anew Mode 0 Control Word is written into the Coun-ter.

GATE e 1 enables counting; GATE e 0 disablescounting. GATE has no effect on OUT.

After the Control Word and initial count are written toa Counter, the initial count will be loaded on the nextCLK pulse. This CLK pulse does not decrement thecount, so for an initial count of N, OUT does not gohigh until N a 1 CLK pulses after the initial count iswritten.

If a new count is written to the Counter, it will beloaded on the next CLK pulse and counting will con-tinue from the new count. If a two-byte count is writ-ten, the following happens:

1) Writing the first byte disables counting. OUT is setlow immediately (no clock pulse required)

2) Writing the second byte allows the new count tobe loaded on the next CLK pulse.

This allows the counting sequence to be synchroniz-ed by software. Again, OUT does not go high untilNa1 CLK pulses after the new count of N is written.

If an initial count is written while GATE e 0, it willstill be loaded on the next CLK pulse. When GATEgoes high, OUT will go high N CLK pulses later; noCLK pulse is needed to load the Counter as this hasalready been done.

MODE 1: HARDWARE RETRIGGERABLEONE-SHOT

OUT will be initially high. OUT will go low on the CLKpulse following a trigger to begin the one-shot pulse,and will remain low until the Counter reaches zero.

OUT will then go high and remain high until the CLKpulse after the next trigger.

After writing the Control Word and initial count, theCounter is armed. A trigger results in loading theCounter and setting OUT low on the next CLK pulse,thus starting the one-shot pulse. An initial count of Nwill result in a one-shot pulse N CLK cycles in dura-tion. The one-shot is retriggerable, hence OUT willremain low for N CLK pulses after any trigger. Theone-shot pulse can be repeated without rewriting thesame count into the counter. GATE has no effect onOUT.

If a new count is written to the Counter during a one-shot pulse, the current one-shot is not affected un-less the counter is retriggered. In that case, theCounter is loaded with the new count and the one-shot pulse continues until the new count expires.

MODE 2: RATE GENERATOR

This Mode functions like a divide-by-N counter. It istypically used to generate a Real Time Clock inter-rupt. OUT will initially be high. When the initial counthas decremented to 1, OUT goes low for one CLKpulse. OUT then goes high again, the Counter re-loads the initial count and the process is repeated.Mode 2 is periodic; the same sequence is repeatedindefinitely. For an initial count of N, the sequencerepeats every N CLK cycles.

GATE e 1 enables counting; GATE e 0 disablescounting. If GATE goes low during an output pulse,OUT is set high immediately. A trigger reloads theCounter with the initial count on the next CLK pulse;OUT goes low N CLK pulses after the trigger. Thusthe GATE input can be used to synchronize theCounter.

After writing a Control Word and initial count, theCounter will be loaded on the next CLK pulse. OUTgoes low N CLK Pulses after the initial count is writ-ten. This allows the Counter to be synchronized bysoftware also.

Writing a new count while counting does not affectthe current counting sequence. If a trigger is re-ceived after writing a new count but before the endof the current period, the Counter will be loaded withthe new count on the next CLK pulse and countingwill continue from the new count. Otherwise, thenew count will be loaded at the end of the currentcounting cycle. In mode 2, a COUNT of 1 is illegal.

MODE 3: SQUARE WAVE MODE

Mode 3 is typically used for Baud rate generation.Mode 3 is similar to Mode 2 except for the duty cycleof OUT. OUT will initially be high. When half the

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231164–7

NOTE:The following conventions apply to all mode timing diagrams:1. Counters are programmed for binary (not BCD) counting and for reading/writing least significant byte (LSB) only.2. The counter is always selected (CS always low).3. CW stands for ‘‘Control Word’’; CW e 10 means a control word of 10 HEX is written to the counter.4. LSB stands for ‘‘Least Significant Byte’’ of count.5. Numbers below diagrams are count values. The lower number is the least significant byte. The upper number is themost significant byte. Since the counter is programmed to read/write LSB only, the most significant byte cannot be read.

N stands for an undefined count.Vertical lines show transitions between count values.

Figure 15. Mode 0

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231164–8

Figure 16. Mode 1

initial count has expired, OUT goes low for the re-mainder of the count. Mode 3 is periodic; the se-quence above is repeated indefinitely. An initialcount of N results in a square wave with a period ofN CLK cycles.

GATE e 1 enables counting; GATE e 0 disablescounting. If GATE goes low while OUT is low, OUT isset high immediately; no CLK pulse is required. Atrigger reloads the Counter with the initial count onthe next CLK pulse. Thus the GATE input can beused to synchronize the Counter.

After writing a Control Word and initial count, theCounter will be loaded on the next CLK pulse. Thisallows the Counter to be synchronized by softwarealso.

Writing a new count while counting does not affectthe current counting sequence. If a trigger is re-ceived after writing a new count but before the endof the current half-cycle of the square wave, theCounter will be loaded with the new count on thenext CLK pulse and counting will continue from the

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231164–9

NOTE:A GATE transition should not occur one clock prior to terminal count.

Figure 17. Mode 2

new count. Otherwise, the new count will be loadedat the end of the current half-cycle.

Mode 3 is implemented as follows:

Even counts: OUT is initially high. The initial count isloaded on one CLK pulse and then is decrementedby two on succeeding CLK pulses. When the countexpires OUT changes value and the Counter is re-loaded with the initial count. The above process isrepeated indefinitely.

Odd counts: OUT is initially high. The initial countminus one (an even number) is loaded on one CLKpulse and then is decremented by two on succeed-ing CLK pulses. One CLK pulse after the count ex-pires, OUT goes low and the Counter is reloadedwith the initial count minus one. Succeeding CLKpulses decrement the count by two. When the countexpires, OUT goes high again and the Counter isreloaded with the initial count minus one. The aboveprocess is repeated indefinitely. So for odd counts,OUT will be high for (N a 1)/2 counts and low for(N b 1)/2 counts.

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231164–10

NOTE:A GATE transition should not occur one clock prior to terminal count.

Figure 18. Mode 3

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MODE 4: SOFTWARE TRIGGERED STROBE

OUT will be initially high. When the initial count ex-pires, OUT will go low for one CLK pulse and thengo high again. The counting sequence is ‘‘triggered’’by writing the initial count.

GATE e 1 enables counting; GATE e 0 disablescounting. GATE has no effect on OUT.

After writing a Control Word and initial count, theCounter will be loaded on the next CLK pulse. ThisCLK pulse does not decrement the count, so for an

initial count of N, OUT does not strobe low until N a

1 CLK pulses after the initial count is written.

If a new count is written during counting, it will beloaded on the next CLK pulse and counting will con-tinue from the new count. If a two-byte count is writ-ten, the following happens:

1) Writing the first byte has no effect on counting.

2) Writing the second byte allows the new count tobe loaded on the next CLK pulse.

This allows the sequence to be ‘‘retriggered’’ bysoftware. OUT strobes low N a 1 CLK pulses afterthe new count of N is written.

231164–11

Figure 19. Mode 4

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MODE 5: HARDWARE TRIGGERED STROBE(RETRIGGERABLE)

OUT will initially be high. Counting is triggered by arising edge of GATE. When the initial count has ex-pired, OUT will go low for one CLK pulse and thengo high again.

After writing the Control Word and initial count, thecounter will not be loaded until the CLK pulse after atrigger. This CLK pulse does not decrement thecount, so for an initial count of N, OUT does notstrobe low until N a 1 CLK pulses after a trigger.

A trigger results in the Counter being loaded with theinitial count on the next CLK pulse. The countingsequence is retriggerable. OUT will not strobe lowfor N a 1 CLK pulses after any trigger. GATE hasno effect on OUT.

If a new count is written during counting, the currentcounting sequence will not be affected. If a triggeroccurs after the new count is written but before thecurrent count expires, the Counter will be loadedwith the new count on the next CLK pulse andcounting will continue from there.

231164–12

Figure 20. Mode 5

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Signal Low

Status Or Going Rising High

Modes Low

0 Disables Ð Ð Enables

Counting Counting

1 Ð Ð 1) Initiates Ð Ð

Counting

2) Resets Output

after Next

Clock

2 1) Disables

Counting Initiates Enables

2) Sets Output Counting Counting

Immediately

High

3 1) Disables

Counting Initiates Enables

2) Sets Output Counting Counting

Immediately

High

4 Disables Ð Ð Enables

Counting Counting

5 Ð Ð Initiates Ð Ð

Counting

Figure 21. Gate Pin Operations Summary

ModeMin Max

Count Count

0 1 0

1 1 0

2 2 0

3 2 0

4 1 0

5 1 0

NOTE:0 is equivalent to 216 for binary counting and 104 forBCD counting.

Figure 22. Minimum and Maximum Initial Counts

Operation Common to All Modes

PROGRAMMING

When a Control Word is written to a Counter, allControl Logic is immediately reset and OUT goes toa known initial state; no CLK pulses are required forthis.

GATE

The GATE input is always sampled on the risingedge of CLK. In Modes 0, 2, 3, and 4 the GATE inputis level sensitive, and the logic level is sampled onthe rising edge of CLK. In Modes 1, 2, 3, and 5 theGATE input is rising-edge sensitive. In these Modes,a rising edge of GATE (trigger) sets an edge-sensi-tive flip-flop in the Counter. This flip-flop is then sam-pled on the next rising edge of CLK; the flip-flop isreset immediately after it is sampled. In this way, atrigger will be detected no matter when it occursÐahigh logic level does not have to be maintained untilthe next rising edge of CLK. Note that in Modes 2and 3, the GATE input is both edge- and level-sensi-tive. In Modes 2 and 3, if a CLK source other thanthe system clock is used, GATE should be pulsedimmediately following WR of a new count value.

COUNTER

New counts are loaded and Counters are decre-mented on the falling edge of CLK.

The largest possible initial count is 0; this is equiva-lent to 216 for binary counting and 104 for BCDcounting.

The Counter does not stop when it reaches zero. InModes 0, 1, 4, and 5 the Counter ‘‘wraps around’’ tothe highest count, either FFFF hex for binary count-ing or 9999 for BCD counting, and continues count-ing. Modes 2 and 3 are periodic; the Counter reloadsitself with the initial count and continues countingfrom there.

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ABSOLUTE MAXIMUM RATINGS*

Ambient Temperature Under Bias ÀÀÀÀÀÀ0§C to 70§CStorage Temperature ÀÀÀÀÀÀÀÀÀÀb65§C to a150§CVoltage on Any Pin with

Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀb0.5V to a7V

Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1W

NOTICE: This is a production data sheet. The specifi-cations are subject to change without notice.

*WARNING: Stressing the device beyond the ‘‘AbsoluteMaximum Ratings’’ may cause permanent damage.These are stress ratings only. Operation beyond the‘‘Operating Conditions’’ is not recommended and ex-tended exposure beyond the ‘‘Operating Conditions’’may affect device reliability.

D.C. CHARACTERISTICS TA e 0§C to 70§C, VCC e 5V g10%

Symbol Parameter Min Max Units Test Conditions

VIL Input Low Voltage b0.5 0.8 V

VIH Input High Voltage 2.0 VCC a0.5V V

VOL Output Low Voltage 0.45 V IOL e 2.0 mA

VOH Output High Voltage 2.4 V IOH e b400 mA

IIL Input Load Current g10 mA VIN e VCC to 0V

IOFL Output Float Leakage g10 mA VOUT e VCC to 0.45V

ICC VCC Supply Current 170 mA

CIN Input Capacitance 10 pF fc e 1 MHz

CI/0 I/O Capacitance 20 pF Unmeasured pins

returned to VSS(4)

A.C. CHARACTERISTICS TA e 0§C to 70§C, VCC e 5V g10%, GND e 0V

Bus Parameters(1)

READ CYCLE

Symbol Parameter8254 8254-2

UnitMin Max Min Max

tAR Address Stable Before RDv 45 30 ns

tSR CS Stable Before RDv 0 0 ns

tRA Address Hold Time After RDu 0 0 ns

tRR RD Pulse Width 150 95 ns

tRD Data Delay from RDv 120 85 ns

tAD Data Delay from Address 220 185 ns

tDF RDu to Data Floating 5 90 5 65 ns

tRV Command Recovery Time 200 165 ns

NOTE:1. AC timings measured at VOH e 2.0V, VOL e 0.8V.

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A.C. CHARACTERISTICS TA e 0§C to 70§C, VCC e 5V g10%, GND e 0V (Continued)

WRITE CYCLE


UnitMin Max Min Max

tAW Address Stable Before WRv 0 0 ns

tSW CS Stable Before WRv 0 0 ns

tWA Address Hold Time After WRv 0 0 ns

tWW WR Pulse Width 150 95 ns

tDW Data Setup Time Before WRu 120 95 ns

tWD Data Hold Time After WRu 0 0 ns

tRV Command Recovery Time 200 165 ns

CLOCK AND GATE


UnitMin Max Min Max

tCLK Clock Period 125 DC 100 DC ns

tPWH High Pulse Width 60(3) 30(3) ns

tPWL Low Pulse Width 60(3) 50(3) ns

tR Clock Rise Time 25 25 ns

tF Clock Fall Time 25 25 ns

tGW Gate Width High 50 50 ns

tGL Gate Width Low 50 50 ns

tGS Gate Setup Time to CLKu 50 40 ns

tGH Gate Setup Time After CLKu 50(2) 50(2) ns

tOD Output Delay from CLKv 150 100 ns

tODG Output Delay from Gatev 120 100 ns

tWC CLK Delay for Loadingv 0 55 0 55 ns

tWG Gate Delay for Sampling b5 50 b5 40 ns

tWO OUT Delay from Mode Write 260 240 ns

tCL CLK Set Up for Count Latch b40 45 b40 40 ns

NOTES:2. In Modes 1 and 5 triggers are sampled on each rising clock edge. A second trigger within 120 ns (70 ns for the 8254-2) ofthe rising clock edge may not be detected.3. Low-going glitches that violate tPWH, tPWL may cause errors requiring counter reprogramming.4. Sampled, not 100% tested. TA e 25§C.5. If CLK present at TWC min then Count equals Na2 CLK pulses, TWC max equals Count Na1 CLK pulse. TWC min toTWC max, count will be either Na1 or Na2 CLK pulses.6. In Modes 1 and 5, if GATE is present when writing a new Count value, at TWG min Counter will not be triggered, at TWGmax Counter will be triggered.7. If CLK present when writing a Counter Latch or ReadBack Command, at TCL min CLK will be reflected in count valuelatched, at TCL max CLK will not be reflected in the count value latched.

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WAVEFORMS

WRITE

231164–13

READ

231164–14

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WAVEFORMS (Continued)

RECOVERY

231164–15

CLOCK AND GATE

231164–16

*Last byte of count being written.

A.C. TESTING INPUT, OUTPUT WAVEFORM

231164–17

A.C. Testing: Inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45Vfor a Logic ‘‘0.’’ Timing measurements are made at 2.0V for aLogic ‘‘1’’ and 0.8V for a Logic ‘‘0’’.

A.C. TESTING LOAD CIRCUIT

231164–18CL e 150 pFCL Includes Jig Capacitance

REVISION SUMMARY

The following list represents the key differences be-tween Rev. 004 and Rev. 005 of the 8254 DataSheet.

1. References to and specifications for the 5 MHz8254-5 are removed. Only the 8 MHz 8254 andthe 10 MHz 8254-2 remain in production.

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December 1988 Order Number: 231468-003

8259APROGRAMMABLE INTERRUPT CONTROLLER

(8259A/8259A-2)

Y 8086, 8088 Compatible

Y MCS-80, MCS-85 Compatible

Y Eight-Level Priority Controller

Y Expandable to 64 Levels

Y Programmable Interrupt Modes

Y Individual Request Mask Capability

Y Single a5V Supply (No Clocks)

Y Available in 28-Pin DIP and 28-LeadPLCC Package(See Packaging Spec., Order Ý231369)

Y Available in EXPRESSÐ Standard Temperature RangeÐ Extended Temperature Range

The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU.It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pinDIP, uses NMOS technology and requires a single a5V supply. Circuitry is static, requiring no clock input.

The 8259A is designed to minimize the software and real time overhead in handling multi-level priority inter-rupts. It has several modes, permitting optimization for a variety of system requirements.

The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operatethe 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered).

231468–1

Figure 1. Block Diagram

DIP

231468–2

PLCC

231468–31

Figure 2. Pin

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Symbol Pin No. Type Name and Function

VCC 28 I SUPPLY: a5V Supply.

GND 14 I GROUND

CS 1 I CHIP SELECT: A low on this pin enables RD and WR communicationbetween the CPU and the 8259A. INTA functions are independent ofCS.

WR 2 I WRITE: A low on this pin when CS is low enables the 8259A to acceptcommand words from the CPU.

RD 3 I READ: A low on this pin when CS is low enables the 8259A to releasestatus onto the data bus for the CPU.

D7–D0 4–11 I/O BIDIRECTIONAL DATA BUS: Control, status and interrupt-vectorinformation is transferred via this bus.

CAS0–CAS2 12, 13, 15 I/O CASCADE LINES: The CAS lines form a private 8259A bus to controla multiple 8259A structure. These pins are outputs for a master 8259Aand inputs for a slave 8259A.

SP/EN 16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin.When in the Buffered Mode it can be used as an output to controlbuffer transceivers (EN). When not in the buffered mode it is used asan input to designate a master (SP e 1) or slave (SP e 0).

INT 17 O INTERRUPT: This pin goes high whenever a valid interrupt request isasserted. It is used to interrupt the CPU, thus it is connected to theCPU’s interrupt pin.

IR0–IR7 18–25 I INTERRUPT REQUESTS: Asynchronous inputs. An interrupt requestis executed by raising an IR input (low to high), and holding it high untilit is acknowledged (Edge Triggered Mode), or just by a high level on anIR input (Level Triggered Mode).

INTA 26 I INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259Ainterrupt-vector data onto the data bus by a sequence of interruptacknowledge pulses issued by the CPU.

A0 27 I AO ADDRESS LINE: This pin acts in conjunction with the CS, WR, andRD pins. It is used by the 8259A to decipher various Command Wordsthe CPU writes and status the CPU wishes to read. It is typicallyconnected to the CPU A0 address line (A1 for 8086, 8088).

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Interrupts in Microcomputer Systems

Microcomputer system design requires that I.O de-vices such as keyboards, displays, sensors and oth-er components receive servicing in a an efficientmanner so that large amounts of the total systemtasks can be assumed by the microcomputer withlittle or no effect on throughput.

The most common method of servicing such devic-es is the Polled approach. This is where the proces-sor must test each device in sequence and in effect‘‘ask’’ each one if it needs servicing. It is easy to seethat a large portion of the main program is loopingthrough this continuous polling cycle and that such amethod would have a serious detrimental effect onsystem throughput, thus limiting the tasks that couldbe assumed by the microcomputer and reducing thecost effectiveness of using such devices.

A more desirable method would be one that wouldallow the microprocessor to be executing its mainprogram and only stop to service peripheral deviceswhen it is told to do so by the device itself. In effect,the method would provide an external asynchronousinput that would inform the processor that it shouldcomplete whatever instruction that is currently beingexecuted and fetch a new routine that will servicethe requesting device. Once this servicing is com-plete, however, the processor would resume exactlywhere it left off.

This method is called Interrupt . It is easy to see thatsystem throughput would drastically increase, andthus more tasks could be assumed by the micro-computer to further enhance its cost effectiveness.

The Programmable Interrupt Controller (PIC) func-tions as an overall manager in an Interrupt-Drivensystem environment. It accepts requests from theperipheral equipment, determines which of the in-coming requests is of the highest importance (priori-ty), ascertains whether the incoming request has ahigher priority value than the level currently beingserviced, and issues an interrupt to the CPU basedon this determination.

Each peripheral device or structure usually has aspecial program or ‘‘routine’’ that is associated withits specific functional or operational requirements;this is referred to as a ‘‘service routine’’. The PIC,after issuing an Interrupt to the CPU, must somehowinput information into the CPU that can ‘‘point’’ theProgram Counter to the service routine associatedwith the requesting device. This ‘‘pointer’’ is an ad-dress in a vectoring table and will often be referredto, in this document, as vectoring data.

231468–3

Figure 3a. Polled Method

231468–4

Figure 3b. Interrupt Method

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8259A

The 8259A is a device specifically designed for usein real time, interrupt driven microcomputer systems.It manages eight levels or requests and has built-infeatures for expandability to other 8259A’s (up to 64levels). It is programmed by the system’s softwareas an I/O peripheral. A selection of priority modes isavailable to the programmer so that the manner inwhich the requests are processed by the 8259A canbe configured to match his system requirements.The priority modes can be changed or reconfigureddynamically at any time during the main program.This means that the complete interrupt structure canbe defined as required, based on the total systemenvironment.

INTERRUPT REQUEST REGISTER (IRR) ANDIN-SERVICE REGISTER (ISR)

The interrupts at the IR input lines are handled bytwo registers in cascade, the Interrupt Request Reg-ister (IRR) and the In-Service (ISR). The IRR is usedto store all the interrupt levels which are requestingservice; and the ISR is used to store all the interruptlevels which are being serviced.

PRIORITY RESOLVER

This logic block determines the priorites of the bitsset in the IRR. The highest priority is selected andstrobed into the corresponding bit of the ISR duringINTA pulse.

INTERRUPT MASK REGISTER (IMR)

The IMR stores the bits which mask the interruptlines to be masked. The IMR operates on the IRR.Masking of a higher priority input will not affect theinterrupt request lines of lower quality.

INT (INTERRUPT)

This output goes directly to the CPU interrupt input.The VOH level on this line is designed to be fullycompatible with the 8080A, 8085A and 8086 inputlevels.

INTA (INTERRUPT ACKNOWLEDGE)

INTA pulses will cause the 8259A to release vector-ing information onto the data bus. The format of thisdata depends on the system mode (mPM) of the8259A.

DATA BUS BUFFER

This 3-state, bidirectional 8-bit buffer is used to inter-face the 8259A to the system Data Bus. Controlwords and status information are transferredthrough the Data Bus Buffer.

READ/WRITE CONTROL LOGIC

The function of this block is to accept OUTput com-mands from the CPU. It contains the InitializationCommand Word (ICW) registers and OperationCommand Word (OCW) registers which store thevarious control formats for device operation. Thisfunction block also allows the status of the 8259A tobe transferred onto the Data Bus.

CS (CHIP SELECT)

A LOW on this input enables the 8259A. No readingor writing of the chip will occur unless the device isselected.

WR (WRITE)

A LOW on this input enables the CPU to write con-trol words (ICWs and OCWs) to the 8259A.

RD (READ)

A LOW on this input enables the 8259A to send thestatus of the Interrupt Request Register (IRR), InService Register (ISR), the Interrupt Mask Register(IMR), or the Interrupt level onto the Data Bus.

A0

This input signal is used in conjunction with WR andRD signals to write commands into the various com-mand registers, as well as reading the various statusregisters of the chip. This line can be tied directly toone of the address lines.

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231468–5

Figure 4a. 8259A Block Diagram

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231468–6

Figure 4b. 8259A Block Diagram

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8259A

THE CASCADE BUFFER/COMPARATOR

This function block stores and compares the IDs ofall 8259A’s used in the system. The associatedthree I/O pins (CAS0-2) are outputs when the 8259Ais used as a master and are inputs when the 8259Ais used as a slave. As a master, the 8259A sendsthe ID of the interrupting slave device onto theCAS0–2 lines. The slave thus selected will send itspreprogrammed subroutine address onto the DataBus during the next one or two consecutive INTApulses. (See section ‘‘Cascading the 8259A’’.)

INTERRUPT SEQUENCE

The powerful features of the 8259A in a microcom-puter system are its programmability and the inter-rupt routine addressing capability. The latter allowsdirect or indirect jumping to the specific interrupt rou-tine requested without any polling of the interruptingdevices. The normal sequence of events during aninterrupt depends on the type of CPU being used.

The events occur as follows in an MCS-80/85 sys-tem:

1. One or more of the INTERRUPT REQUEST lines(IR7–0) are raised high, setting the correspond-ing IRR bit(s).

2. The 8259A evaluates these requests, and sendsan INT to the CPU, if appropriate.

3. The CPU acknowledges the INT and respondswith an INTA pulse.

4. Upon receiving an INTA from the CPU group, thehighest priority ISR bit is set, and the correspond-ing IRR bit is reset. The 8259A will also release aCALL instruction code (11001101) onto the 8-bitData Bus through its D7–0 pins.

5. This CALL instruction will initiate two more INTApulses to be sent to the 8259A from the CPUgroup.

6. These two INTA pulses allow the 8259A to re-lease its preprogrammed subroutine addressonto the Data Bus. The lower 8-bit address is re-

leased at the first INTA pulse and the higher 8-bitaddress is released at the second INTA pulse.

7. This completes the 3-byte CALL instruction re-leased by the 8259A. In the AEOI mode the ISRbit is reset at the end of the third INTA pulse.Otherwise, the ISR bit remains set until an appro-priate EOI command is issued at the end of theinterrupt sequence.

The events occuring in an 8086 system are thesame until step 4.

4. Upon receiving an INTA from the CPU group, thehighest priority ISR bit is set and the correspond-ing IRR bit is reset. The 8259A does not drive theData Bus during this cycle.

5. The 8086 will initiate a second INTA pulse. Dur-ing this pulse, the 8259A releases an 8-bit pointeronto the Data Bus where it is read by the CPU.

6. This completes the interrupt cycle. In the AEOImode the ISR bit is reset at the end of the sec-ond INTA pulse. Otherwise, the ISR bit remainsset until an appropriate EOI command is issuedat the end of the interrupt subroutine.

If no interrupt request is present at step 4 of eithersequence (i.e., the request was too short in duration)the 8259A will issue an interrupt level 7. Both thevectoring bytes and the CAS lines will look like aninterrupt level 7 was requested.

When the 8259A PIC receives an interrupt, INT be-comes active and an interrupt acknowledge cycle isstarted. If a higher priority interrupt occurs betweenthe two INTA pulses, the INT line goes inactive im-mediately after the second INTA pulse. After an un-specified amount of time the INT line is activatedagain to signify the higher priority interrupt waitingfor service. This inactive time is not specified andcan vary between parts. The designer should beaware of this consideration when designing a sys-tem which uses the 8259A. It is recommended thatproper asynchronous design techniques be fol-lowed.

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231468–7

Figure 4c. 8259A Block Diagram

231468–8

Figure 5. 8259A Interface to

Standard System Bus

INTERRUPT SEQUENCE OUTPUTS

MCS-80, MCS-85

This sequence is timed by three INTA pulses. Duringthe first INTA pulse the CALL opcode is enabledonto the data bus.

Content of First Interrupt Vector Byte

D7 D6 D5 D4 D3 D2 D1 D0

CALL CODE 1 1 0 0 1 1 0 1

During the second INTA pulse the lower address ofthe appropriate service routine is enabled onto thedata bus. When Interval e 4 bits A5–A7 are pro-grammed, while A0–A4 are automatically inserted bythe 8259A. When Interval e 8 only A6 and A7 areprogrammed, while A0–A5 are automatically insert-ed.

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Content of Second Interrupt Vector Byte

IR Interval e 4

D7 D6 D5 D4 D3 D2 D1 D0

7 A7 A6 A5 1 1 1 0 0

6 A7 A6 A5 1 1 0 0 0

5 A7 A6 A5 1 0 1 0 0

4 A7 A6 A5 1 0 0 0 0

3 A7 A6 A5 0 1 1 0 0

2 A7 A6 A5 0 1 0 0 0

1 A7 A6 A5 0 0 1 0 0

0 A7 A6 A5 0 0 0 0 0

IR Interval e 8

D7 D6 D5 D4 D3 D2 D1 D0

7 A7 A6 1 1 1 0 0 0

6 A7 A6 1 1 0 0 0 0

5 A7 A6 1 0 1 0 0 0

4 A7 A6 1 0 0 0 0 0

3 A7 A6 0 1 1 0 0 0

2 A7 A6 0 1 0 0 0 0

1 A7 A6 0 0 1 0 0 0

0 A7 A6 0 0 0 0 0 0

During the third INTA pulse the higher address of theappropriate service routine, which was programmedas byte 2 of the initialization sequence (A8–A15), isenabled onto the bus.

Content of Third Interrupt Vector Byte

D7 D6 D5 D4 D3 D2 D1 D0

A15 A14 A13 A12 A11 A10 A9 A8

8086, 8088

8086 mode is similar to MCS-80 mode except thatonly two Interrupt Acknowledge cycles are issued bythe processor and no CALL opcode is sent to theprocessor. The first interrupt acknowledge cycle issimilar to that of MCS-80, 85 systems in that the8259A uses it to internally freeze the state of theinterrupts for priority resolution and as a master itissues the interrupt code on the cascade lines at theend of the INTA pulse. On this first cycle it does notissue any data to the processor and leaves its databus buffers disabled. On the second interrupt ac-knowledge cycle in 8086 mode the master (or slaveif so programmed) will send a byte of data to theprocessor with the acknowledged interrupt code

composed as follows (note the state of the ADImode control is ignored and A5–A11 are unused in8086 mode):

Content of Interrupt Vector Byte

for 8086 System Mode

D7 D6 D5 D4 D3 D2 D1 D0

IR7 T7 T6 T5 T4 T3 1 1 1

IR6 T7 T6 T5 T4 T3 1 1 0

IR5 T7 T6 T5 T4 T3 1 0 1

IR4 T7 T6 T5 T4 T3 1 0 0

IR3 T7 T6 T5 T4 T3 0 1 1

IR2 T7 T6 T5 T4 T3 0 1 0

IR1 T7 T6 T5 T4 T3 0 0 1

IR0 T7 T6 T5 T4 T3 0 0 0

PROGRAMMING THE 8259A

The 8259A accepts two types of command wordsgenerated by the CPU:

1. Initialization Command Words (ICWs): Beforenormal operation can begin, each 8259A in thesystem must be brought to a starting pointÐby asequence of 2 to 4 bytes timed by WR pulses.

2. Operation Command Words (OCWs): These arethe command words which command the 8259Ato operate in various interrupt modes. Thesemodes are:

a. Fully nested mode

b. Rotating priority mode

c. Special mask mode

d. Polled mode

The OCWs can be written into the 8259A anytimeafter initialization.

INITIALIZATION COMMAND WORDS(ICWS)

General

Whenever a command is issued with A0 e 0 and D4e 1, this is interpreted as Initialization CommandWord 1 (ICW1). ICW1 starts the intiitalization se-quence during which the following automatically oc-cur.

a. The edge sense circuit is reset, which means thatfollowing initialization, an interrupt request (IR) in-put must make a low-to-high transistion to gener-ate an interrupt.

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b. The Interrupt Mask Register is cleared.

c. IR7 input is assigned priority 7.

d. The slave mode address is set to 7.

e. Special Mask Mode is cleared and Status Read isset to IRR.

f. If IC4 e 0, then all functions selected in ICW4are set to zero. (Non-Buffered mode*, no Auto-EOI, MCS-80, 85 system).

*NOTE:Master/Slave in ICW4 is only used in the bufferedmode.

Initialization Command Words 1 and 2(ICW1, ICW2)

A5–A15: Page starting address of service routines .In an MCS 80/85 system, the 8 request levels willgenerate CALLs to 8 locations equally spaced inmemory. These can be programmed to be spaced atintervals of 4 or 8 memory locations, thus the 8 rou-tines will occupy a page of 32 or 64 bytes, respec-tively.

The address format is 2 bytes long (A0–A15). Whenthe routine interval is 4, A0–A4 are automatically in-serted by the 8259A, while A5–A15 are programmedexternally. When the routine interval is 8, A0–A5 areautomatically inserted by the 8259A, while A6–A15are programmed externally.

The 8-byte interval will maintain compatibility withcurrent software, while the 4-byte interval is best fora compact jump table.

In an 8086 system A15–A11 are inserted in the fivemost significant bits of the vectoring byte and the8259A sets the three least significant bits accordingto the interrupt level. A10–A5 are ignored and ADI(Address interval) has no effect.

LTIM: If LTIM e 1, then the 8259A will operate inthe level interrupt mode. Edge detect logicon the interrupt inputs will be disabled.

ADI: CALL address interval. ADI e 1 then inter-val e 4; ADI e 0 then interval e 8.

SNGL: Single. Means that this is the only 8259A inthe system. If SNGL e 1 no ICW3 will beissued.

IC4: If this bit is setÐICW4 has to be read. IfICW4 is not needed, set IC4 e 0.

Initialization Command Word 3 (ICW3)

This word is read only when there is more than one8259A in the system and cascading is used, in which

case SNGL e 0. It will load the 8-bit slave register.The functions of this register are:

a. In the master mode (either when SP e 1, or inbuffered mode when M/S e 1 in ICW4) a ‘‘1’’ isset for each slave in the system. The master thenwill release byte 1 of the call sequence (for MCS-80/85 system) and will enable the correspondingslave to release bytes 2 and 3 (for 8086 only byte2) through the cascade lines.

b. In the slave mode (either when SP e 0, or if BUFe 1 and M/S e 0 in ICW4) bits 2–0 identify theslave. The slave compares its cascade input withthese bits and, if they are equal, bytes 2 and 3 ofthe call sequence (or just byte 2 for 8086) arereleased by it on the Data Bus.

231468–9

Figure 6. Initialization Sequence

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Initialization Command Word 4 (ICW4)SFNM: If SFNM e 1 the special fully nested mode

is programmed.

BUF: If BUF e 1 the buffered mode is pro-grammed. In buffered mode SP/EN be-comes an enable output and the master/slave determination is by M/S.

M/S: If buffered mode is selected: M/S e 1means the 8259A is programmed to be a

master, M/S e 0 means the 8259A is pro-grammed to be a slave. If BUF e 0, M/Shas no function.

AEOI: If AEOI e 1 the automatic end of interruptmode is programmed.

mPM: Microprocessor mode: mPM e 0 sets the8259A for MCS-80, 85 system operation,mPM e 1 sets the 8259A for 8086 systemoperation.

231468–10

231468–11

Figure 7. Initialization Command Word Format

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231468–12

231468–13

231468–14

NOTE:Slave ID is equal to the corresponding master IR input.

Figure 7. Initialization Command Word Format (Continued)

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OPERATION COMMAND WORDS(OCWS)

After the Initialization Command Words (ICWs) areprogrammed into the 8259A, the chip is ready to ac-cept interrupt requests at its input lines. However,during the 8259A operation, a selection of algo-rithms can command the 8259A to operate in vari-ous modes through the Operation Command Words(OCWs).

Operation Control Words (OCWs)OCW1

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 M7 M6 M5 M4 M3 M2 M1 M0

OCW2

0 R SL EOI 0 0 L2 L1 L0

OCW3

0 0 ESMM SMM 0 1 P RR RIS

231468–15

231468–16

Figure 8. Operation Command Word Format

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Operation Control Word 1 (OCW1)

OCW1 sets and clears the mask bits in the interruptMask Register (IMR). M7–M0 represent the eightmask bits. M e 1 indicates the channel is masked(inhibited), M e 0 indicates the channel is enabled.


R, SL, EOIÐThese three bits control the Rotate andEnd of Interrupt modes and combinations of the two.A chart of these combinations can be found on theOperation Command Word Format.

L2, L1, L0ÐThese bits determine the interrupt levelacted upon when the SL bit is active.

231468–17

Figure 8. Operation Command Word Format (Continued)

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ESMMÐEnable Special Mask Mode. When this bitis set to 1 it enables the SMM bit to set or reset theSpecial Mask Mode. When ESMM e 0 the SMM bitbecomes a ‘‘don’t care’’.

SMMÐSpecial Mask Mode. If ESMM e 1 and SMMe 1 the 8259A will enter Special Mask Mode. IfESMM e 1 and SMM e 0 the 8259A will revert tonormal mask mode. When ESMM e 0, SMM has noeffect.

Fully Nested Mode

This mode is entered after initialization unless anoth-er mode is programmed. The interrupt requests areordered in priority from 0 through 7 (0 highest).When an interrupt is acknowledged the highest pri-ority request is determined and its vector placed onthe bus. Additionally, a bit of the Interrupt Serviceregister (ISO-7) is set. This bit remains set until themicroprocessor issues an End of Interrupt (EOI)command immediately before returning from theservice routine, or if AEOI (Automatic End of Inter-rupt) bit is set, until the trailing edge of the last INTA.While the IS bit is set, all further interrupts of thesame or lower priority are inhibited, while higher lev-els will generate an interrupt (which will be acknowl-edged only if the microprocessor internal Interuptenable flip-flop has been re-enabled through soft-ware).

After the initialization sequence, IR0 has the highestprioirity and IR7 the lowest. Priorities can bechanged, as will be explained, in the rotating prioritymode.

End of Interrupt (EOI)

The In Service (IS) bit can be reset either automati-cally following the trailing edge of the last in se-quence INTA pulse (when AEOI bit in ICW1 is set) orby a command word that must be issued to the8259A before returning from a service routine (EOIcommand). An EOI command must be issued twiceif in the Cascade mode, once for the master andonce for the corresponding slave.

There are two forms of EOI command: Specific andNon-Specific. When the 8259A is operated in modeswhich perserve the fully nested structure, it can de-termine which IS bit to reset on EOI. When a Non-Specific EOI command is issued the 8259A will auto-matically reset the highest IS bit of those that areset, since in the fully nested mode the highest ISlevel was necessarily the last level acknowledgedand serviced. A non-specific EOI can be issued withOCW2 (EOI e 1, SL e 0, R e 0).

When a mode is used which may disturb the fullynested structure, the 8259A may no longer be ableto determine the last level acknowledged. In thiscase a Specific End of Interrupt must be issuedwhich includes as part of the command the IS levelto be reset. A specific EOI can be issued with OCW2(EOI e 1, SL e 1, R e 0, and L0–L2 is the binarylevel of the IS bit to be reset).

It should be noted that an IS bit that is masked by anIMR bit will not be cleared by a non-specific EOI ifthe 8259A is in the Special Mask Mode.

Automatic End of Interrupt (AEOI)Mode

If AEOI e 1 in ICW4, then the 8259A will operate inAEOI mode continuously until reprogrammed byICW4. in this mode the 8259A will automatically per-form a non-specific EOI operation at the trailingedge of the last interrupt acknowledge pulse (thirdpulse in MCS-80/85, second in 8086). Note thatfrom a system standpoint, this mode should be usedonly when a nested multilevel interrupt structure isnot required within a single 8259A.

The AEOI mode can only be used in a master 8259Aand not a slave. 8259As with a copyright date of1985 or later will operate in the AEOI mode as amaster or a slave.

Automatic Rotation(Equal Priority Devices)

In some applications there are a number of interrupt-ing devices of equal priority. In this mode a device,after being serviced, receives the lowest priority, soa device requesting an interrupt will have to wait, inthe worst case until each of 7 other devices areserviced at most once. For example, if the priorityand ‘‘in service’’ status is:

Before Rotate (IR4 the highest prioirity requiringservice)

‘‘IS’’ Status 231468–18

Priority Status 231468–19

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After Rotate (IR4 was serviced, all other prioritiesrotated correspondingly)

‘‘IS’’ Status 231468–20

Priority Status 231468–21

There are two ways to accomplish Automatic Rota-tion using OCW2, the Rotation on Non-Specific EOICommand (R e 1, SL e 0, EOI e 1) and the Ro-tate in Automatic EOI Mode which is set by (R e 1,SL e 0, EOI e 0) and cleared by (R e 0, SL e 0,EOI e 0).

Specific Rotation(Specific Priority)

The programmer can change priorities by program-ming the bottom priority and thus fixing all other pri-orities; i.e., if IR5 is programmed as the bottom prior-ity device, then IR6 will have the highest one.

The Set Priority command is issued in OCW2 where:R e 1, SL e 1, L0–L2 is the binary priority levelcode of the bottom priority device.

Observe that in this mode internal status is updatedby software control during OCW2. However, it is in-dependent of the End of Interrupt (EOI) command(also executed by OCW2). Priority changes can beexecuted during an EOI command by using the Ro-tate on Specific EOI command in OCW2 (R e 1, SLe 1, EOI e 1 and LO–L2 e IR level to receivebottom priority).

Interrupt Masks

Each Interrupt Request input can bem masked indi-vidually by the Interrupt Mask Register (IMR) pro-grammed through OCW1. Each bit in the IMR masksone interrupt channel if it is set (1). Bit 0 masks IR0,Bit 1 masks IR1 and so forth. Masking an IR channeldoes not affect the other channels operation.

Special Mask Mode

Some applications may require an interrupt serviceroutine to dynamically alter the system priority struc-

ture during its execution under software control. Forexample, the routine may wish to inhibit lower priori-ty requests for a portion of its execution but enablesome of them for another portion.

The difficulty here is that if an Interrupt Request isacknowledged and an End of Interrupt command didnot reset its IS bit (i.e., while executing a serviceroutine), the 8259A would have inhibited all lowerpriority requests with no easy way for the routine toenable them.

That is where the Special Mask Mode comes in. Inthe special Mask Mode, when a mask bit is set inOCW1, it inhibits further interrupts at that level andenables interrupts fromall other levels (lower as wellas higher) that are not masked.

Thus, any interrupts may be selectively enabled byloading the mask register.

The special Mask Mode is set by OWC3 where:SSMM e 1, SMM e 1, and cleared where SSMM e

1, SMM e 0.

Poll Command

In Poll mode the INT output functions as it normallydoes. The microprocessor should ignore this output.This can be accomplished either by not connectingthe INT output or by masking interrupts within themicroprocessor, thereby disabling its interrupt input.Service to devices is achieved by software using aPoll command.

The Poll command is issued by setting P e ‘1’’ inOCW3. The 8259A treats the next RD pulse to the8259A (i.e., RD e 0, CS e 0) as an interrupt ac-knowledge, sets the appropriate IS bit if there is arequest, and reads the priority level. Interrupt is fro-zen from WR to RD.

The word enabled onto the data bus during RD is:

D7 D6 D5 D4 D3 D2 D1 D0

I Ð Ð Ð Ð W2 W1 W0

W0–W2: Binary code of the highest priority levelrequesting service.

I: Equal to ‘‘1’’ if there is an interrupt.

This mode is useful if there is a routine commandcommon to several levels so that the INTA se-quence is not needed (saves ROM space). Anotherapplication is to use the poll mode to expand thenumber of priority levels to more than 64.

Reading the 8259A Status

The input status of several internal registers can beread to update the user information on the system.

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NOTES:231468–22

1. Master clear active only during ICW1.2. FREEZE is active during INTA and poll sequences only.3. Truth Table for a D-Latch.

C D Q Operation

1 Di Di Follow0 X Qn-1 Hold

Figure 9. Priority CellÐSimplified Logic Diagram

The following registers can be read via OCW3 (IRRand ISR or OCW1 [IMR]).

Interrupt Request Register (IRR): 8-bit register whichcontains the levels requesting an interrupt to be ac-knowledged. The highest request level is reset fromthe IRR when an interrupt is acknowledged. (Not af-fected by IMR.)

In-Service Register (ISR): 8-bit register which con-tains the priority levels that are being serviced. TheISR is updated when an End of Interrupt Commandis issued.

Interrupt Mask Register: 8-bit register which con-tains the interrupt request lines which are masked.

The IRR can be read when, prior to the RD pulse, aRead Register Command is issued with OCW3 (RRe 1, RIS e 0.)

The ISR can be read, when, prior to the RD pulse, aRead Register Command is issued with OCW3 (RRe 1, RIS e 1).

There is no need to write an OCW3 before everystatus read operation, as long as the status readcorresponds with the previous one; i.e., the 8259A‘‘remembers’’ whether the IRR or ISR has been pre-viously selected by the OCW3. This is not true whenpoll is used.

After initialization the 8259A is set to IRR.

For reading the IMR, no OCW3 is needed. The out-put data bus will contain the IMR whenever RD isactive and A0 e 1 (OCW1).

Polling overrides status read when P e 1, RR e 1in OCW3.

Edge and Level Triggered Modes

This mode is programmed using bit 3 in ICW1.

If LTIM e ‘0’, an interrupt request will be recognizedby a low to high transition on an IR input. The IRinput can remain high without generating another in-terrupt.

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231468–23

Figure 10. IR Triggering Timing Requirements

If LTIM e ‘1’, an interrupt request will be recognizedby a ‘high’ level on IR Input, and there is no need foran edge detection. The interrupt request must beremoved before the EOI command is issued or theCPU interrupts is enabled to prevent a second inter-rupt from occurring.

The priority cell diagram shows a conceptual circuitof the level sensitive and edge sensitive input circuit-ry of the 8259A. Be sure to note that the requestlatch is a transparent D type latch.

In both the edge and level triggered modes the IRinputs must remain high until after the falling edge ofthe first INTA. If the IR input goes low before thistime a DEFAULT IR7 will occur when the CPU ac-knowledges the interrupt. This can be a useful safe-guard for detecting interrupts caused by spuriousnoise glitches on the IR inputs. To implement thisfeature the IR7 routine is used for ‘‘clean up’’ simplyexecuting a return instruction, thus ignoring the inter-rupt. If IR7 is needed for other purposes a defaultIR7 can still be detected by reading the ISR. A nor-mal IR7 interrupt will set the corresponding ISR bit, adefault IR7 won’t. If a default IR7 routine occurs dur-ing a normal IR7 routine, however, the ISR will re-main set. In this case it is necessary to keep track ofwhether or not the IR7 routine was previously en-tered. If another IR7 occurs it is a default.

The Special Fully Nest Mode

This mode will be used in the case of a big systemwhere cascading is used, and the priority has to beconserved within each slave. In this case the fullynested mode will be programmed to the master (us-

ing ICW4). This mode is similar to the normal nestedmode with the following exceptions:

a. When an interrupt request from a certain slave isin service this slave is not locked out from themaster’s priority logic and further interrupt re-quests from higher priority IR’s within the slavewill be recognized by the master and will initiateinterrupts to the processor. (In the normal nestedmode a slave is masked out when its request is inservice and no higher requests from the sameslave can be serviced.)

b. When exiting the Interrupt Service routine thesoftware has to check whether the interrupt serv-iced was the only one from that slave. This isdone by sending a non-specific End of Interrupt(EOI) command to the slave and then reading itsIn-Service register and checking for zero. If it isempty, a non-specific EOI can be sent to themaster too. If not, no EOI should be sent.

Buffered Mode

When the 8259A is used in a large system wherebus driving buffers are required on the data bus andthe cascading mode is used, there exists the prob-lem of enabling buffers.

The buffered mode will structure the 8259A to sendan enable signal on SP/EN to enable the buffers. Inthis mode, whenever the 8259A’s data bus outputsare enabled, the SP/EN output becomes active.

This modification forces the use of software pro-gramming to determine whether the 8259A is a mas-ter or a slave. Bit 3 in ICW4 programs the bufferedmode, and bit 2 in ICW4 determines whether it is amaster or a slave.

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CASCADE MODE

The 8259A can be easily interconnected in a systemof one master with up to eight slaves to handle up to64 priority levels.

The master controls the slaves through the 3 linecascade bus. The cascade bus acts like chip selectsto the slaves during the INTA sequence.

In a cascade configuration, the slave interrupt out-puts are connected to the master interrupt requestinputs. When a slave request line is activated andafterwards acknowledged, the master will enable thecorresponding slave to release the device routineaddress during bytes 2 and 3 of INTA. (Byte 2 onlyfor 8086/8088).

The cascade bus lines are normally low and will con-tain the slave address code from the trailing edge ofthe first INTA pulse to the trailing edge of the thirdpulse. Each 8259A in the system must follow a sep-arate initialization sequence and can be pro-grammed to work in a different mode. An EOI com-mand must be issued twice: once for the master andonce for the corresponding slave. An address de-coder is required to activate the Chip Select (CS)input of each 8259A.

The cascade lines of the Master 8259A are activat-ed only for slave inputs, non-slave inputs leave thecascade line inactive (low).

231468–24

Figure 11. Cascading the 8259A

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Ambient Temperature Under Bias ÀÀÀÀÀÀ0§C to 70§CStorage Temperature ÀÀÀÀÀÀÀÀÀÀb65§C to a150§CVoltage on Any Pin

with Respect to GroundÀÀÀÀÀÀÀÀÀÀb0.5V to a7V

Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1W



D.C. CHARACTERISTICS TA e 0§C to 70§C, VCC e 5V g 10%

Symbol Parameter Min Max Units Test Conditions

VIL Input Low Voltage b0.5 0.8 V

VIH Input High Voltage 2.0* VCC a 0.5V V

VOL Output Low Voltage 0.45 V IOL e 2.2 mA


VOH(INT) Interrupt Output High 3.5 V IOH eb100 mA

Voltage2.4 V IOH e b400 mA

ILI Input Load Current b10 a10 mA 0V s VIN s VCC

ILOL Output Leakage Current b10 a10 mA 0.45V s VOUT s VCC

ICC VCC Supply Current 85 mA

ILIR IR Input Load Current b300 mA VIN e 0

10 mA VIN e VCC

*NOTE:For Extended Temperature EXPRESS VIH e 2.3V.

CAPACITANCE TA e 25§C; VCC e GND e 0V

Symbol Parameter Min Typ Max Unit Test Conditions

CIN Input Capacitance 10 pF fc e 1 MHz

CI/O I/O Capacitance 20 pF Unmeasured Pins Returned to VSS

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A.C. CHARACTERISTICS TA e 0§C to 70§C, VCC e 5V g10%

TIMING REQUIREMENTS

Symbol Parameter8259A 8259A-2

Units Test ConditionsMin Max Min Max

TAHRL AO/CS Setup to RD/INTAv 0 0 ns

TRHAX AO/CS Hold after RD/INTAu 0 0 ns

TRLRH RD Pulse Width 235 160 ns

TAHWL AO/CS Setup to WRv 0 0 ns

TWHAX AO/CS Hold after WRu 0 0 ns

TWLWH WR Pulse Width 290 190 ns

TDVWH Data Setup to WRu 240 160 ns

TWHDX Data Hold after WRu 0 0 ns

TJLJH Interrupt Request Width (Low) 100 100 ns See Note 1

TCVIAL Cascade Setup to Second or Third55 40 ns

INTAv (Slave Only)

TRHRL End of RD to Next RD

End of INTA to Next INTA within 160 100 ns

an INTA Sequence Only

TWHWL End of WR to Next WR 190 100 ns

*TCHCL End of Command to Next Command500 150 ns

(Not Same Command Type)

End of INTA Sequence to Next500 300

INTA Sequence.

*Worst case timing for TCHCL in an actual microprocessor system is typically much greater than 500 ns (i.e. 8085A e

1.6 ms, 8085A-2 e 1 ms, 8086 e 1 ms, 8086-2 e 625 ns)

NOTE:This is the low time required to clear the input latch in the edge triggered mode.

TIMING RESPONSES

Symbol Parameter8259A 8259A-2

Units Test ConditionsMin Max Min Max

TRLDV Data Valid from RD/INTAv200 120 ns

C of Data Bus e

100 pF

TRHDZ Data Float after RD/INTAu 10 100 10 85 ns C of Data Bus

TJHIH Interrupt Output Delay 350 300 nsMax Test C e 100 pF

TIALCV Cascade Valid from First INTAv565 360 ns CINT e 100 pF

Min Test C e 15 pF

(Master Only)

TRLEL Enable Active from RDv or INTAv 125 100 nsCCASCADE e 100 pF

TRHEH Enable Inactive from RDu or INTAu 150 150 ns

TAHDV Data Valid from Stable Address 200 200 ns

TCVDV Cascade Valid to Valid Data 300 200 ns

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8259A

A.C. TESTING INPUT/OUTPUT WAVEFORM

231468–25

A.C. Testing: Inputs are driven at 2.4V for a logic ‘‘1’’ and 0.45Vfor a logic ‘‘0’’. Timing measurements are made at 2.0V for a logic‘‘1’’ and 0.8V for a logic ‘‘0’’.

A.C. TESTING LOAD CIRCUIT

231468–26

CL e 100 pFCL Includes Jig Capacitance

WAVEFORMS

WRITE

231468–27

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8259A


READ/INTA

231468–28

OTHER TIMING

231468–29

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8259A


INTA SEQUENCE

231468–30

NOTES:Interrupt output must remain HIGH at least until leading edge of first INTA.1. Cycle 1 in 8086, 8088 systems, the Data Bus is not active.

Data Sheet Revision Review

The following changes have been made since revision 2 of the 8259A data sheet.

1. The first paragraph of the Poll Command section was rewritten to clarify the status of the INT pin.

2. A paragraph was added to the Interrupt Sequence section to indicate the status of the INT pin duringmultiple interrupts.

3. A reference to PLCC packaging was added.

4. All references to the 8259A-8 have been deleted.

INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. (408) 765-8080

INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. (0793) 696 000

INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511

Printed in U.S.A./xxxx/1196/B10M/xx xx

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September 1993 Order Number: 231466-005

8237AHIGH PERFORMANCE

PROGRAMMABLE DMA CONTROLLER(8237A-5)

Y Enable/Disable Control of IndividualDMA Requests

Y Four Independent DMA Channels

Y Independent Autoinitialization of AllChannels

Y Memory-to-Memory Transfers

Y Memory Block Initialization

Y Address Increment or Decrement

Y High Performance: Transfers up to1.6M Bytes/Second with 5 MHz 8237A-5

Y Directly Expandable to Any Number ofChannels

Y End of Process Input for TerminatingTransfers

Y Software DMA Requests

Y Independent Polarity Control for DREQand DACK Signals

Y Available in EXPRESSÐ Standard Temperature Range

Y Available in 40-Lead Cerdip and PlasticPackages(See Packaging Spec, Order Ý231369)

The 8237A Multimode Direct Memory Access (DMA) Controller is a peripheral interface circuit for microproc-essor systems. It is designed to improve system performance by allowing external devices to directly transferinformation from the system memory. Memory-to-memory transfer capability is also provided. The 8237Aoffers a wide variety of programmable control features to enhance data throughput and system optimizationand to allow dynamic reconfiguration under program control.

The 8237A is designed to be used in conjunction with an external 8-bit address latch. It contains four indepen-dent channels and may be expanded to any number of channels by cascading additional controller chips. Thethree basic transfer modes allow programmability of the types of DMA service by the user. Each channel canbe individually programmed to Autoinitialize to its original condition following an End of Process (EOP). Eachchannel has a full 64K address and word count capability.

231466–2

Figure 2. Pin

Configuration231466–1

Figure 1. Block Diagram

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Symbol Type Name and Function

VCC POWER: a5V supply.

VSS GROUND: Ground.

CLK I CLOCK INPUT: Clock Input controls the internal operations of the8237A and its rate of data transfers. The input may be driven at upto 5 MHz for the 8237A-5.

CS I CHIP SELECT: Chip Select is an active low input used to selectthe 8237A as an I/O device during the Idle cycle. This allows CPUcommunication on the data bus.

RESET I RESET: Reset is an active high input which clears the Command,Status, Request and Temporary registers. It also clears the first/last flip/flop and sets the Mask register. Following a Reset thedevice is in the Idle cycle.

READY I READY: Ready is an input used to extend the memory read andwrite pulses from the 8237A to accommodate slow memories orI/O peripheral devices. Ready must not make transitions during itsspecified setup/hold time.

HLDA I HOLD ACKNOWLEDGE: The active high Hold Acknowledge fromthe CPU indicates that it has relinquished control of the systembusses.

DREQ0–DREQ3 I DMA REQUEST: The DMA Request lines are individualasynchronous channel request inputs used by peripheral circuits toobtain DMA service. In fixed Priority, DREQ0 has the highestpriority and DREQ3 has the lowest priority. A request is generatedby activating the DREQ line of a channel. DACK will acknowledgethe recognition of DREQ signal. Polarity of DREQ isprogrammable. Reset initializes these lines to active high. DREQmust be maintained until the corresponding DACK goes active.

DB0–DB7 I/O DATA BUS: The Data Bus lines are bidirectional three-statesignals connected to the system data bus. The outputs areenabled in the Program condition during the I/O Read to outputthe contents of an Address register, a Status register, theTemporary register or a Word Count register to the CPU. Theoutputs are disabled and the inputs are read during an I/O Writecycle when the CPU is programming the 8237A control registers.During DMA cycles the most significant 8 bits of the address areoutput onto the data bus to be strobed into an external latch byADSTB. In memory-to-memory operations, data from the memorycomes into the 8237A on the data bus during the read-from-memory transfer. In the write-to-memory transfer, the data busoutputs place the data into the new memory location.

IOR I/O I/O READ: I/O Read is a bidirectional active low three-state line.In the Idle cycle, it is an input control signal used by the CPU toread the control registers. In the Active cycle, it is an output controlsignal used by the 8237A to access data from a peripheral during aDMA Write transfer.

IOW I/O I/O WRITE: I/O Write is a bidirectional active low three-state line.In the Idle cycle, it is an input control signal used by the CPU toload information into the 8237A. In the Active cycle, it is an outputcontrol signal used by the 8237A to load data to the peripheralduring a DMA Read transfer.

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8237A

Table 1. Pin Description (Continued)

Symbol Type Name and Function

EOP I/O END OF PROCESS: End of Process is an active low bidirectionalsignal. Information concerning the completion of DMA services isavailable at the bidirectional EOP pin. The 8237A allows anexternal signal to terminate an active DMA service. This isaccomplished by pulling the EOP input low with an external EOPsignal. The 8237A also generates a pulse when the terminal count(TC) for any channel is reached. This generates an EOP signalwhich is output through the EOP line. The reception of EOP, eitherinternal or external, will cause the 8237A to terminate the service,reset the request, and, if Autoinitialize is enabled, to write the baseregisters to the current registers of that channel. The mask bit andTC bit in the status word will be set for the currently active channelby EOP unless the channel is programmed for Autoinitialize. In thatcase, the mask bit remains unchanged. During memory-to-memorytransfers, EOP will be output when the TC for channel 1 occurs.EOP should be tied high with a pull-up resistor if it is not used toprevent erroneous end of process inputs.

A0–A3 I/O ADDRESS: The four least significant address lines arebidirectional three-state signals. In the Idle cycle they are inputsand are used by the CPU to address the register to be loaded orread. In the Active cycle they are outputs and provide the lower 4bits of the output address.

A4–A7 O ADDRESS: The four most significant address lines are three-stateoutputs and provide 4 bits of address. These lines are enabledonly during the DMA service.

HRQ O HOLD REQUEST: This is the Hold Request to the CPU and isused to request control of the system bus. If the correspondingmask bit is clear, the presence of any valid DREQ causes 8237A toissue the HRQ.

DACK0–DACK3 O DMA ACKNOWLEDGE: DMA Acknowledge is used to notify theindividual peripherals when one has been granted a DMA cycle.The sense of these lines is programmable. Reset initializes themto active low.

AEN O ADDRESS ENABLE: Address Enable enables the 8-bit latchcontaining the upper 8 address bits onto the system address bus.AEN can also be used to disable other system bus drivers duringDMA transfers. AEN is active HIGH.

ADSTB O ADDRESS STROBE: The active high, Address Strobe is used tostrobe the upper address byte into an external latch.

MEMR O MEMORY READ: The Memory Read signal is an active low three-state output used to access data from the selected memorylocation during a DMA Read or a memory-to-memory transfer.

MEMW O MEMORY WRITE: The Memory Write is an active low three-stateoutput used to write data to the selected memory location during aDMA Write or a memory-to-memory transfer.

PIN5 I PIN5: This pin should always be at a logic HIGH level. An internalpull-up resistor will establish a logic high when the pin is leftfloating. It is recommended however, that PIN5 be connected toVCC.

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8237A


The 8237A block diagram includes the major logicblocks and all of the internal registers. The data in-terconnection paths are also shown. Not shown arethe various control signals between the blocks. The8237A contains 344 bits of internal memory in theform of registers. Figure 3 lists these registers byname and shows the size of each. A detailed de-scription of the registers and their functions can befound under Register Description.

Name Size Number

Base Address Registers 16 bits 4Base Word Count Registers 16 bits 4Current Address Registers 16 bits 4Current Word Count Registers 16 bits 4Temporary Address Register 16 bits 1Temporary Word Count Register 16 bits 1Status Register 8 bits 1Command Register 8 bits 1Temporary Register 8 bits 1Mode Registers 6 bits 4Mask Register 4 bits 1Request Register 4 bits 1

Figure 3. 8237A Internal Registers

The 8237A contains three basic blocks of controllogic. The Timing Control block generates internaltiming and external control signals for the 8237A.The Program Command Control block decodes thevarious commands given to the 8237A by the micro-processor prior to servicing a DMA Request. It alsodecodes the Mode Control word used to select thetype of DMA during the servicing. The Priority En-coder block resolves priority contention betweenDMA channels requesting service simultaneously.

The Timing Control block derives internal timingfrom the clock input. In 8237A systems, this inputwill usually be the w2 TTL clock from an 8224 orCLK from an 8085AH or 8284A. 33% duty cycleclock generators, however, may not meet the clockhigh time requirement of the 8237A of the same fre-quency. For example, 82C84A-5 CLK output violatesthe clock high time requirement of 8237A-5. In thiscase 82C84A CLK can simply be inverted to meet8237A-5 clock high and low time requirements. For8085AH-2 systems above 3.9 MHz, the 8085CLK(OUT) does not satisfy 8237A-5 clock LOW andHIGH time requirements. In this case, an externalclock should be used to drive the 8237A-5.

DMA OPERATION

The 8237A is designed to operate in two major cy-cles. These are called Idle and Active cycles. Eachdevice cycle is made up of a number of states. The8237A can assume seven separate states, eachcomposed of one full clock period. State I (SI) is theinactive state. It is entered when the 8237A has no

valid DMA requests pending. While in SI, the DMAcontroller is inactive but may be in the Program Con-dition, being programmed by the processor. StateS0 (S0) is the first state of a DMA service. The8237A has requested a hold but the processor hasnot yet returned an acknowledge. The 8237A maystill be programmed until it receives HLDA from theCPU. An acknowledge from the CPU will signal thatDMA transfers may begin. S1, S2, S3 and S4 are theworking states of the DMA service. If more time isneeded to complete a transfer than is available withnormal timing, wait states (SW) can be inserted be-tween S2 or S3 and S4 by the use of the Ready lineon the 8237A. Note that the data is transferred di-rectly from the I/O device to memory (or vice versa)with IOR and MEMW (or MEMR and IOW) being ac-tive at the same time. The data is not read into ordriven out of the 8237A in I/O-to-memory or memo-ry-to-I/O DMA transfers.

Memory-to-memory transfers require a read-fromand a write-to-memory to complete each transfer.The states, which resemble the normal workingstates, use two digit numbers for identification. Eightstates are required for a single transfer. The first fourstates (S11, S12, S13, S14) are used for the read-from-memory half and the last four states (S21, S22,S23, S24) for the write-to-memory half of the trans-fer.

IDLE CYCLE

When no channel is requesting service, the 8237Awill enter the Idle cycle and perform ‘‘SI’’ states. Inthis cycle the 8237A will sample the DREQ lines ev-ery clock cycle to determine if any channel is re-questing a DMA service. The device will also sampleCS, looking for an attempt by the microprocessor towrite or read the internal registers of the 8237A.When CS is low and HLDA is low, the 8237A entersthe Program Condition. The CPU can now establish,change or inspect the internal definition of the partby reading from or writing to the internal registers.Address lines A0–A3 are inputs to the device andselect which registers will be read or written. TheIOR and IOW lines are used to select and time readsor writes. Due to the number and size of the internalregisters, an internal flip-flop is used to generate anadditional bit of address. This bit is used to deter-mine the upper or lower byte of the 16-bit Addressand Word Count registers. The flip-flop is reset byMaster Clear or Reset. A separate software com-mand can also reset this flip-flop.

Special software commands can be executed by the8237A in the Program Condition. These commandsare decoded as sets of addresses with the CS andIOW. The commands do not make use of the databus. Instructions include Clear First/Last Flip-Flopand Master Clear.

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8237A

ACTIVE CYCLE

When the 8237A is in the Idle cycle and a non-masked channel requests a DMA service, the devicewill output an HRQ to the microprocessor and enterthe Active cycle. It is in this cycle that the DMA serv-ice will take place, in one of four modes:

Single Transfer ModeÐIn Single Transfer modethe device is programmed to make one transfer only.The word count will be decremented and the ad-dress decremented or incremented following eachtransfer. When the word count ‘‘rolls over’’ from zeroto FFFFH, a Terminal Count (TC) will cause an Auto-initialize if the channel has been programmed to doso.

DREQ must be held active until DACK becomes ac-tive in order to be recognized. If DREQ is held activethroughout the single transfer, HRQ will go inactiveand release the bus to the system. It will again goactive and, upon receipt of a new HLDA, anothersingle transfer will be performed. In 8080A, 8085AH,8088, or 8086 system, this will ensure one full ma-chine cycle execution between DMA transfers. De-tails of timing between the 8237A and other buscontrol protocols will depend upon the characteris-tics of the microprocessor involved.

Block Transfer ModeÐIn Block Transfer mode thedevice is activated by DREQ to continue makingtransfers during the service until a TC, caused byword count going to FFFFH, or an external End of

Process (EOP) is encountered. DREQ need only beheld active until DACK becomes active. Again, anAutoinitialization will occur at the end of the serviceif the channel has been programmed for it.

Demand Transfer ModeÐIn Demand Transfermode the device is programmed to continue makingtransfers until a TC or external EOP is encounteredor until DREQ goes inactive. Thus transfers maycontinue until the I/O device has exhausted its datacapacity. After the I/O device has had a chance tocatch up, the DMA service is re-established bymeans of a DREQ. During the time between serviceswhen the microprocessor is allowed to operate, theintermediate values of address and word count arestored in the 8237A Current Address and CurrentWord Count registers. Only an EOP can cause anAutoinitialize at the end of the service. EOP is gener-ated either by TC or by an external signal. DREQhas to be low before S4 to prevent another Transfer.

Cascade ModeÐThis mode is used to cascademore than one 8237A together for simple systemexpansion. The HRQ and HLDA signals from the ad-ditional 8237A are connected to the DREQ andDACK signals of a channel of the initial 8237A. Thisallows the DMA requests of the additional device topropagate through the priority network circuitry ofthe preceding device. The priority chain is preservedand the new device must wait for its turn to acknowl-edge requests. Since the cascade channel of theinitial 8237A is used only for prioritizing the addition-al device, it does not output any address or control

231466–3

Figure 4. Cascaded 8237As

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8237A

signals of its own. These could conflict with the out-puts of the active channel in the added device. The8237A will respond to DREQ and DACK but all otheroutputs except HRQ will be disabled. The ready in-put is ignored.

Figure 4 shows two additional devices cascaded intoan initial device using two of the previous channels.This forms a two level DMA system. More 8237Ascould be added at the second level by using theremaining channels of the first level. Additional de-vices can also be added by cascading into the chan-nels of the second level device, forming a third level.

TRANSFER TYPES

Each of the three active transfer modes can performthree different types of transfers. These are Read,Write and Verify. Write transfers move data from anI/O device to the memory by activating MEMW andIOR. Read transfers move data from memory to anI/O device by activating MEMR and IOW. Verifytransfers are pseudo transfers. The 8237A operatesas in Read or Write transfers generating addresses,and responding to EOP, etc. However, the memoryand I/O control lines all remain inactive. The readyinput is ignored in verify mode.

Memory-to-MemoryÐTo perform block moves ofdata from one memory address space to anotherwith a minimum of program effort and time, the8237A includes a memory-to-memory transfer fea-ture. Programming a bit in the Command registerselects channels 0 and 1 to operate as memory-to-memory transfer channels. The transfer is initiatedby setting the software DREQ for channel 0. The8237A requests a DMA service in the normal man-ner. After HLDA is true, the device, using four statetransfers in Block Transfer mode, reads data fromthe memory. The channel 0 Current Address registeris the source for the address used and is decrement-ed or incremented in the normal manner. The databyte read from the memory is stored in the 8237Ainternal Temporary register. Channel 1 then per-forms a four-state transfer of the data from the Tem-porary register to memory using the address in itsCurrent Address register and incrementing or decre-menting it in the normal manner. The channel 1 cur-rent Word Count is decremented. When the wordcount of channel 1 goes to FFFFH, a TC is generat-ed causing an EOP output terminating the service.

Channel 0 may be programmed to retain the sameaddress for all transfers. This allows a single word tobe written to a block of memory.

The 8237A will respond to external EOP signals dur-ing memory-to-memory transfers. Data comparatorsin block search schemes may use this input to termi-nate the service when a match is found. The timingof memory-to-memory transfers is found in Figure12. Memory-to-memory operations can be detectedas an active AEN with no DACK outputs.

AutoinitializeÐBy programming a bit in the Moderegister, a channel may be set up as an Autoinitializechannel. During Autoinitialize initialization, the origi-nal values of the Current Address and Current WordCount registers are automatically restored from theBase Address and Base Word count registers of thatchannel following EOP. The base registers are load-ed simultaneously with the current registers by themicroprocessor and remain unchanged throughoutthe DMA service. The mask bit is not altered whenthe channel is in Autoinitialize. Following Autoinitial-ize the channel is ready to perform another DMAservice, without CPU intervention, as soon as a validDREQ is detected. In order to Autoinitialize bothchannels in a memory-to-memory transfer, bothword counts should be programmed identically. If in-terrupted externally, EOP pulses should be appliedin both bus cycles.

PriorityÐThe 8237A has two types of priority en-coding available as software selectable options. Thefirst is Fixed Priority which fixes the channels in pri-ority order based upon the descending value of theirnumber. The channel with the lowest priority is 3followed by 2, 1 and the highest priority channel, 0.After the recognition of any one channel for service,the other channels are prevented from interferingwith that service until it is completed.

After completion of a service, HRQ will go inactiveand the 8237A will wait for HLDA to go low beforeactivating HRQ to service another channel.

The second scheme is Rotating Priority. The lastchannel to get service becomes the lowest prioritychannel with the others rotating accordingly.

231466–4

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With Rotating Priority in a single chip DMA system,any device requesting service is guaranteed to berecognized after no more than three higher priorityservices have occurred. This prevents any onechannel from monopolizing the system.

Compressed TimingÐIn order to achieve evengreater throughput where system characteristicspermit, the 8237A can compress the transfer time totwo clock cycles. From Figure 11 it can be seen thatstate S3 is used to extend the access time of theread pulse. By removing state S3, the read pulsewidth is made equal to the write pulse width and atransfer consists only of state S2 to change the ad-dress and state S4 to perform the read/write. S1states will still occur when A8–A15 need updating(see Address Generation). Timing for compressedtransfers is found in Figure 14.

Address GenerationÐIn order to reduce pin count,the 8237A multiplexes the eight higher order ad-dress bits on the data lines. State S1 is used to out-put the higher order address bits to an external latchfrom which they may be placed on the address bus.The falling edge of Address Strobe (ADSTB) is usedto load these bits from the data lines to the latch.Address Enable (AEN) is used to enable the bitsonto the address bus through a three-state enable.The lower order address bits are output by the8237A directly. Lines A0–A7 should be connectedto the address bus. Figure 11 shows the time rela-tionships between CLK, AEN, ADSTB, DB0–DB7and A0–A7.

During Block and Demand Transfer mode services,which include multiple transfers, the addresses gen-erated will be sequential. For many transfers thedata held in the external address latch will remainthe same. This data need only change when a carryor borrow from A7 to A8 takes place in the normalsequence of addresses. To save time and speedtransfers, the 8237A executes S1 states only whenupdating of A8–A15 in the latch is necessary. Thismeans for long services, S1 states and AddressStrobes may occur only once every 256 transfers, asavings of 255 clock cycles for each 256 transfers.

REGISTER DESCRIPTION

Current Address RegisterÐEach channel has a16-bit Current Address register. This register holdsthe value of the address used during DMA transfers.The address is automatically incremented or decre-mented after each transfer and the intermediate val-ues of the address are stored in the Current Addressregister during the transfer. This register is written orread by the microprocessor in successive 8-bitbytes. It may also be reinitialized by an Autoinitializeback to its original value. Autoinitialize takes placeonly after an EOP.

Current Word RegisterÐEach channel has a 16-bit Current Word Count register. This register deter-mines the number of transfers to be performed. Theactual number of transfers will be one more than thenumber programmed in the Current Word Count reg-ister (i.e., programming a count of 100 will result in101 transfers). The word count is decremented aftereach transfer. The intermediate value of the wordcount is stored in the register during the transfer.When the value in the register goes from zero toFFFFH, a TC will be generated. This register is load-ed or read in successive 8-bit bytes by the micro-processor in the Program Condition. Following theend of a DMA service it may also be reinitialized byan Autoinitialization back to its original value. Auto-initialize can occur only when an EOP occurs. If it isnot Autoinitialized, this register will have a count ofFFFFH after TC.

Base Address and Base Word Count RegistersÐEach channel has a pair of Base Address and BaseWord Count registers. These 16-bit registers storethe original value of their associated current regis-ters. During Autoinitialize these values are used torestore the current registers to their original values.The base registers are written simultaneously withtheir corresponding current register in 8-bit bytes inthe Program Condition by the microprocessor.These registers cannot be read by the microproces-sor.

Command RegisterÐThis 8-bit register controlsthe operation of the 8237A. It is programmed by themicroprocessor in the Program Condition and iscleared by Reset or a Master Clear instruction. Thefollowing table lists the function of the commandbits. See Figure 6 for address coding.

Mode RegisterÐEach channel has a 6-bit Moderegister associated with it. When the register is beingwritten to by the microprocessor in the ProgramCondition, bits 0 and 1 determine which channelMode register is to be written.

Request RegisterÐThe 8237A can respond to re-quests for DMA service which are initiated by soft-ware as well as by a DREQ. Each channel has arequest bit associated with it in the 4-bit Requestregister. These are non-maskable and subject to pri-oritization by the Priority Encoder network. Each reg-ister bit is set or reset separately under softwarecontrol or is cleared upon generation of a TC or ex-ternal EOP. The entire register is cleared by a Reset.To set or reset a bit, the software loads the properform of the data word. See Figure 5 for register ad-dress coding. In order to make a software request,the channel must be in Block Mode.

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Command Register

231466–5

Mode Register

231466–6

Request Register

231466–7

Mask RegisterÐEach channel has associated withit a mask bit which can be set to disable the incom-ing DREQ. Each mask bit is set when its associatedchannel produces an EOP if the channel is not pro-grammed for Autoinitialize. Each bit of the 4-bitMask register may also be set or cleared separatelyunder software control. The entire register is also setby a Reset. This disables all DMA requests until aclear Mask register instruction allows them to occur.The instruction to separately set or clear the maskbits is similar in form to that used with the Requestregister. See Figure 5 for instruction addressing.

231466–8

All four bits of the Mask register may also be writtenwith a single command.

231466–9

Register OperationSignals

CS IOR IOW A3 A2 A1 A0

Command Write 0 1 0 1 0 0 0

Mode Write 0 1 0 1 0 1 1

Request Write 0 1 0 1 0 0 1

Mask Set/Reset 0 1 0 1 0 1 0

Mask Write 0 1 0 1 1 1 1

Temporary Read 0 0 1 1 1 0 1

Status Read 0 0 1 1 0 0 0

Figure 5. Definition of Register Codes

Status RegisterÐThe Status register is available tobe read out of the 8237A by the microprocessor. Itcontains information about the status of the devicesat this point. This information includes which chan-nels have reached a terminal count and which chan-

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231466–10

nels have pending DMA requests. Bits 0–3 are setevery time a TC is reached by that channel or anexternal EOP is applied. These bits are cleared uponReset and on each Status Read. Bits 4–7 are setwhenever their corresponding channel is requestingservice.

Temporary RegisterÐThe Temporary register isused to hold data during memory-to-memory trans-fers. Following the completion of the transfers, thelast word moved can be read by the microprocessorin the Program Condition. The Temporary registeralways contains the last byte transferred in the previ-ous memory-to-memory operation, unless clearedby a Reset.

Software CommandsÐThese are additional spe-cial software commands which can be executed inthe Program Condition. They do not depend on anyspecific bit pattern on the data bus. The three soft-ware commands are:

Clear First/Last Flip-Flop: This command must beexecuted prior to writing or reading new addressor word count information to the 8237A. This ini-tializes the flip-flop to a known state so that sub-sequent accesses to register contents by the mi-croprocessor will address upper and lower bytesin the correct sequence.

Master Clear: This software instruction has thesame effect as the hardware Reset. The Com-mand, Status, Request, Temporary, and InternalFirst/Last Flip-Flop registers are cleared and theMask register is set. The 8237A will enter the Idlecycle.

Clear Mask Register: This command clears themask bits of all four channels, enabling them toaccept DMA requests.

Figure 6 lists the address codes for the softwarecommands.

SignalsOperation

A3 A2 A1 A0 IOR IOW

1 0 0 0 0 1 Read Status Register

1 0 0 0 1 0 Write Command Register

1 0 0 1 0 1 Illegal

1 0 0 1 1 0 Write Request Register

1 0 1 0 0 1 Illegal

1 0 1 0 1 0 Write Single Mask Register Bit

1 0 1 1 0 1 Illegal

1 0 1 1 1 0 Write Mode Register

1 1 0 0 0 1 Illegal

1 1 0 0 1 0 Clear Byte Pointer Flip/Flop

1 1 0 1 0 1 Read Temporary Register

1 1 0 1 1 0 Master Clear

1 1 1 0 0 1 Illegal

1 1 1 0 1 0 Clear Mask Register

1 1 1 1 0 1 Illegal

1 1 1 1 1 0 Write All Mask Register Bits

Figure 6. Software Command Codes

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Channel Register OperationSignals Internal Data Bus

CS IOR IOW A3 A2 A1 A0 Flip-Flop DB0–DB7

0 Base and Current Address Write 0 1 0 0 0 0 0 0 A0–A7

0 1 0 0 0 0 0 1 A8–A15

Current Address Read 0 0 1 0 0 0 0 0 A0–A7

0 0 1 0 0 0 0 1 A8–A15

Base and Current Word Count Write 0 1 0 0 0 0 1 0 W0–W7

0 1 0 0 0 0 1 1 W8–W15

Current Word Count Read 0 0 1 0 0 0 1 0 W0–W7

0 0 1 0 0 0 1 1 W8–W15


0 1 0 0 0 1 0 1 A8–A15


0 0 1 0 0 1 0 1 A8–A15


0 1 0 0 0 1 1 1 W8–W15


0 0 1 0 0 1 1 1 W8–W15


0 1 0 0 1 0 0 1 A8–A15


0 0 1 0 1 0 0 1 A8–A15


0 1 0 0 1 0 1 1 W8–W15


0 0 1 0 1 0 1 1 W8–W15


0 1 0 0 1 1 0 1 A8–A15


0 0 1 0 1 1 0 1 A8–A15


0 1 0 0 1 1 1 1 W8–W15


0 0 1 0 1 1 1 1 W8–W15

Figure 7. Word Count and Address Register Command Codes

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PROGRAMMING

The 8237A will accept programming from the hostprocessor any time that HLDA is inactive; this is trueeven if HRQ is active. The responsibility of the hostis to assure that programming and HLDA are mutual-ly exclusive. Note that a problem can occur if a DMArequest occurs, on an unmasked channel while the8237A is being programmed. For instance, the CPUmay be starting to reprogram the two byte Addressregister of channel 1 when channel 1 receives aDMA request. If the 8237A is enabled (bit 2 in thecommand register is 0) and channel 1 is unmasked,a DMA service will occur after only one byte of theAddress register has been reprogrammed. This canbe avoided by disabling the controller (setting bit 2 inthe command register) or masking the channel be-fore programming any other registers. Once the pro-gramming is complete, the controller can be en-abled/unmasked.

After power-up it is suggested that all internal loca-tions, especially the Mode registers, be loaded withsome valid value. This should be done even if some

channels are unused. An invalid mode may force allcontrol signals to go active at the same time.

APPLICATION INFORMATION (Note 1)

Figure 8 shows a convenient method for configuringa DMA system with the 8237A controller and an8080A/8085AH microprocessor system. The multi-mode DMA controller issues a HRQ to the processorwhenever there is at least one valid DMA requestfrom a peripheral device. When the processor re-plies with a HLDA signal, the 8237A takes control ofthe address bus, the data bus and the control bus.The address for the first transfer operation comesout in two bytesÐthe least significant 8 bits on theeight address outputs and the most significant 8 bitson the data bus. The contents of the data bus arethen latched into an 8-bit latch to complete the full16 bits of the address bus. The 8282 is a highspeed, 8-bit, three-state latch in a 20-pin package.After the initial transfer takes place, the latch is up-dated only after a carry or borrow is generated in theleast significant address byte. Four DMA channelsare provided when one 8237A is used.

231466–11

Figure 8. 8237A System Interface

NOTE:1. See Application Note AP-67 for 8086 design information.

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Ambient Temperature under Bias ÀÀÀÀÀÀ0§C to 70§CCase Temperature ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§C to a75§CStorage Temperature ÀÀÀÀÀÀÀÀÀÀb65§C to a150§CVoltage on Any Pin with

Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀb0.5V to a7V

Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5 Watt



D.C. CHARACTERISTICSTA e 0§C to 70§C, TCASE e 0§C to 75§C, VCC e a5.0V g5%, GND e 0V

Symbol Parameter MinTyp

Max Unit Test Conditions(Note 1)


3.3 V IOH e b100 mA (HRQ Only)

VOL Output LOW Voltage 0.40 V IOL e 3.2 mA

VIH Input HIGH Voltage 2.0 VCC a 0.5 V

VIL Input LOW Voltage b0.5 0.8 V

ILI Input Load Current g10 mA 0V s VIN s VCC

ILO Output Leakage Current g10 mA 0.45V s VOUT s VCC

ICC VCC Supply Current 110 130 mA TA e a25§C130 150 mA TA e 0§C

CO Output Capacitance 4 8 pF

CI Input Capacitance 8 15 pF fc e 1.0 MHz, Inputs e 0V

CIO I/O Capacitance 10 18 pF

NOTE:1. Typical values are for TA e 25§C, nominal supply voltage and nominal processing parameters.

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A.C. CHARACTERISTICSÐDMA (MASTER) MODETA e 0§C to 70§C, TCASE e 0§C to 75§C, VCC e a5V g5%, GND e 0V

Symbol Parameter8237A-5

UnitMin Max

TAEL AEN HIGH from CLK LOW (S1) Delay Time 200 ns

TAET AEN LOW from CLK HIGH (SI) Delay Time 130 ns

TAFAB ADR Active to Float Delay from CLK HIGH 90 ns

TAFC READ or WRITE Float from CLK HIGH 120 ns

TAFDB DB Active to Float Delay from CLK HIGH 170 ns

TAHR ADR from READ HIGH Hold Time TCY-100 ns

TAHS DB from ADSTB LOW Hold Time 30 ns

TAHW ADR from WRITE HIGH Hold Time TCY-50 ns

TAK DACK Valid from CLK LOW Delay Time (Note 1)220 170 ns

EOP HIGH from CLK HIGH Delay Time (Note 2) 170 ns

EOP LOW from CLK HIGH Delay Time 170 ns

TASM ADR Stable from CLK HIGH 170 ns

TASS DB to ADSTB LOW Setup Time 100 ns

TCH Clock High Time (Transitionss10 ns) 80 ns

TCL Clock LOW Time (Transitionss10 ns) 68 ns

TCY CLK Cycle Time 200 ns

TDCL CLK HIGH to READ or WRITE LOW Delay (Note 3) 190 ns

TDCTR READ HIGH from CLK HIGH 190 ns

(S4) Delay Time (Note 3)

TDCTW WRITE HIGH from CLK HIGH 130 ns

(S4) Delay Time (Note 3)

TDQ1 HRQ Valid from CLK HIGH Delay Time (Note 4) 120 ns

TDQ2 120 ns

TEPS EOP LOW from CLK LOW Setup Time 40 ns

TEPW EOP Pulse Width 220 ns

TFAAB ADR Float to Active Delay from CLK HIGH 170 ns

TFAC READ or WRITE Active from CLK HIGH 150 ns

TFADB DB Float to Active Delay from CLK HIGH 200 ns

THS HLDA Valid to CLK HIGH Setup Time 75 ns

TIDH Input Data from MEMR HIGH Hold Time 0 ns

TIDS Input Data to MEMR HIGH Setup Time 170 ns

TODH Output Data from MEMW HIGH Hold Time 10 ns

TODV Output Data Valid to MEMW HIGH 125 ns

TQS DREQ to CLK LOW (SI, S4) Setup Time (Note 1) 0 ns

TRH CLK to READY LOW Hold Time 20 ns

TRS READY to CLK LOW Setup Time 60 ns

TSTL ADSTB HIGH from CLK HIGH Delay Time 130 ns

TSTT ADSTB LOW from CLK HIGH Delay Time 90 ns

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A.C. CHARACTERISTICSÐPERIPHERAL (SLAVE) MODETA e 0§C to 70§C, TCASE e 0§C to 75§C, VCC e a5V g5%, GND e 0V

Symbol Parameter8237A-5

UnitMin Max

TAR ADR Valid or CS LOW to READ LOW 50 ns

TAW ADR Valid to WRITE HIGH Setup Time 130 ns

TCW CS LOW to WRITE HIGH Setup Time 130 ns

TDW Data Valid to WRITE HIGH Setup Time 130 ns

TRA ADR or CS Hold from READ HIGH 0 ns

TRDE Data Access from READ LOW (Note 5) 140 ns

TRDF DB Float Delay from READ HIGH 0 70 ns

TRSTD Power Supply HIGH to RESET LOW Setup Time 500 ns

TRSTS RESET to First IOWR 2TCY ns

TRSTW RESET Pulse Width 300 ns

TRW READ Width 200 ns

TWA ADR from WRITE HIGH Hold Time 20 ns

TWC CS HIGH from WRITE HIGH Hold Time 20 ns

TWD Data from WRITE HIGH Hold Time 30 ns

TWWS Write Width 160 ns

TWR End of Write to End of Read in DMA Transfer 0 ns

NOTES:1. DREQ and DACK signals may be active high or active low. Timing diagrams assume the active high mode.2. EOP is an open collector output. This parameter assumes the presence of a 2.2K pullup to VCC.3. The net IOW or MEMW Pulse width for normal write will be TCYb100 ns and for extended write will be 2TCYb100 ns.The net IOR or MEMR pulse width for normal read will be 2TCYb50 ns and for compressed read will be TCYb50 ns.4. TDQ is specified for two different output HIGH levels. TDQ1 is measured at 2.0V. TDQ2 is measured at 3.3V. The valuefor TDQ2 assumes an external 3.3 KX pull-up resistor connected from HRQ to VCC.5. Output Loading on the Data Bus is 1 TTL Gate plus 100 pF capacitance.

A.C. TESTING INPUT/OUTPUT WAVEFORM

231466–12A.C. Testing: Inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45Vfor a Logic ‘‘0.’’ Timing measurements are made at 2.0V for aLogic ‘‘1’’ and 0.8V for a Logic ‘‘0.’’ Input timing parameters as-sume transition times of 20 ns or less. Waveform measurementpoints for both input and output signals are 2.0V for HIGH and0.8V for LOW, unless otherwise noted.

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WAVEFORMS

SLAVE MODE WRITE TIMING

231466–13

NOTE:1. Successive read and/or write operations by the external processor to program or examine the controller must betimed to allow at least 400 ns for the 8237A-5 as recovery time between active read or write pulses. The same recoverytime is needed between an active read or write pulse followed by a DMA transfer.

Figure 9. Slave Mode Write

SLAVE MODE READ TIMING

231466–14

NOTE:1. Successive read and/or write operations by the external processor to program or examine the controller must betimed to allow at least 400 ns for the 8237A-5 as recovery time between active read or write pulses. The same recoverytime is needed between an active read or write pulse followed by a DMA transfer.

Figure 10. Slave Mode Read

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DMA TRANSFER TIMING

231466–15

NOTE:1. DREQ should be held active until DACK is returned.

Figure 11. DMA Transfer

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MEMORY-TO-MEMORY TRANSFER TIMING

231466–16

Figure 12. Memory-to-Memory Transfer

READY TIMING

231466–17

Figure 13. Ready

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COMPRESSED TRANSFER TIMING

231466–18

Figure 14. Compressed Transfer

RESET TIMING

231466–19

Figure 15. Reset

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8237A

DESIGN CONSIDERATIONS

1. Cascading from channel zero. When using mul-tiple 8237s, always start cascading with channelzero. Channel zero of the 8237 will operate incor-rectly if one or more of channels 1, 2, or 3 areused in the cascade mode while channel zero isused in a mode other than cascade.

2. Do not treat the DREQ signal as an asynchro-nous input while the channel is in the ‘‘de-mand’’ or ‘‘cascade’’ modes. If DREQ becomesinactive at any time during state S4, an illegalstate may occur causing the 8237 to operate im-properly.

3. HRQ must remain active until HLDA becomesactive. If HRQ goes inactive before HLDA is re-ceived the 8237 can enter an illegal state causingit to operate improperly.

4. Make sure the MEMRÝ line has 50 pF loadingcapacitance on it. When doing memory to mem-ory transfers, the 8237 requires at least 50 pFloading capacitance on the MEMRÝ signal forproper operation. In most cases board capaci-tance is sufficient.

5. Treat the READY input as a synchronous in-put. If a transition occurs during the setup/holdwindow, erratic operation may result.

6. Any channel in cascade mode should have anactive DREQ before a HRQ.

DATA SHEET REVISION REVIEW

The following list represents key differences be-tween this and the -003 data sheet. Please reviewthis summary carefully.

1. Item 6 was added to the ‘‘Design Considerations’’section.

REVISION SUMMARY

The following list represents the key differences be-tween rev. 004 and rev. 005 of the 1994 8237A DataSheet.

1. References to and specifications for the 8237Aand 8237A-4 are removed. Only the 8237A-5 5 MHzdevice remains in production.

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electronica digital aplicada

Engineering