cuestiones_vhdl_basico

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VHDL Bsico

I. Introduction Section Questions(The slides for these questions start at Slide 18.)

I.1. VHDL is a hardware description language that can be used to describe designs at various levels ofabstractions. Which of the following system descriptions (from the a!s"i and #uhn $%&hart' aredirectly supported by VHDL

a' )ehavioral *odelb' +tructural *odelc' ,hysical-eometry *odeld' ll the above

e' a and b only

I./. 0he VHDL language was developed under an Institute of lectrical and lectronic ngineers(I' committee initiative as a standardi2ed language for describing hardware and software.

a' 0rueb' 3alse

II. Desin !"a#$le Section Questions

(The slides for these questions start at Slide %&.)

II.1. VHDL *odel which instantiates components and then interconnects them with each other(and with the outside world' by attaching signals using ,450 *,+ most li"ely represents which ofthe following styles of VHDL model

a' )ehavioral +pecificationb' Data 3low +pecificationc' +tructural +pecification

II./. VHDL *odel which uses abstracts constructs (such as If%0hen%lse' most li"ely representswhich of the following styles of VHDL model

a. )ehavioral +pecificationb. Data 3low +pecificationc. +tructural +pecification

II.6. VHDL *odel that e7clusively uses concurrent signal assignment statements to describe thefunctionality of the design most li"ely represents which of the following styles of VHDL model

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11. )ehavioral +pecification1/. Data 3low +pecification16. +tructural +pecification

II. detailed models of physical hardware ta"e much longer tosimulate than abstract or algorithmic models. Which of the following VHDL modeling styles willresult in the shortest simulation times

1. +tructural model/. Dataflow (50L' model6. )ehavioral model

II.?. Which style of VHDL *odel is most appropriate for use during the early stages of a design

c' +tructural model (because components can be easily added and removed'd' Dataflow (50L' model (because logic e=uations can be easily manipulated for design

modifications'

e' )ehavioral model (because it is implementation independent'f' *i7ture of all three methods (because the appropriate level of abstraction can be chosen which

is best suited for our design'

III. 'odel o#$onents Section Questions(The slides for these questions start at Slide .)

III.1. Which of the following is the most accurate statement about VHDL entities and architectures

1. component can have many entity declarations and many architectures./. component can have many entity declarations but only one architecture.

6. component can have only one entity declaration and many alternative architectures.


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III.


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6. wire integer> physical and floating point are scalar typesc' arrays and record types are composite typesd' the "ey difference between variables and signals is the assignment delay

IV.?. Which of the following statements about ob!ects is incorrect or inaccurate

a. 4b!ects declared in a pac"age are available to all VHDL descriptions that usethatpac"age

b. 4b!ects declared in an entity are available to all architectures associated with that

entityc. 4b!ects declared in an architecture body are available to all statements in that

architectured. 4b!ects declared in a process are available to all processes in the architecture body

IV.E. Which of the following is not a correct or accurate statement about constants

1. &4C+0C0 perfectFscoreJ C0B5L JK 1;;is an e7ample of a constant declaration

/. 0he assignment of the value to a constant can be done in a pac"age

6. 0he value of a constant must be assigned at the time the constant is declared present and future values and their assignment is done after a certain delay.

?. signalsE. variables:. constants9. files

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IV.8. VHDL FFFFFFFF ob!ects are used for te7t input and output> and provide a way for the designto communicate with the host environment.

a' signalb' variablec' filed' constant

IV.1;. Which of the following statements are true

a' ll VHDL processes e7ecute concurrentlyb' &oncurrent signal assignment statements are one%line processesc' +tatements in a process e7ecute se=uentiallyd' ll of the above

IV.11. Which of the following statements are true

1?. ,ac"ages and libraries provide the ability to reuse constructs in multiple entities andarchitectures

1E. Items declared in pac"ages can be used(i.e. included' in other VHDL components1:. ,ac"ages consist of two parts> namely the pac"age declaration and the pac"age body19. ll of the above

IV.1/. 0he following fragment of VHDL code illustrates the use of what construct

I3 cloc"Gevent CD cloc" K 1G 0HCoutput K input M1

CD I3

a' attributesb' cloc"sc' commentsd' identifiers

IV.16 Logical operators have FFFFFFFFF compared to other operators

1. lowest precedence/. highest precedence6. medium precedence


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IV.1 "eyboard> dis"Fdrive> printer'e' none of the above

IV.1?. Which of the following is a correct VHDL integer type declaration

a. &4C+0C0 temp J integer JK 1;;b. +ICL 7 J integer JK ?c. V5I)L var J integer JK /;d. ll of the above

IV.1E. 0he VHDL 5ecord composite data type is used to group elements of FFFFFFFFF types into asingle VHDL ob!ect.

a' similarb' differentc' identicald' integere' floating point

V. VHDL !"a#$les Section Questions

1;V.1. With reference to the VHDL code segment> which of the following statements is mostaccurate

5&HI0&0B5 testFbehav 43 test I+

V5I)L 7 J )I0 JK 1G

)IC,54&++ ( inFsig> y'

+ICL y J )I0 JK ;G)IC

N JK inFsig N45 y$ K inFsig N45 7

CD ,54&++CD testFbehav

a' variable (7' is incorrectly declared in the process declaration section

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b' signal (y' is incorrectly defined in the architecture declaration sectionc' )oth the Variable and +ignal declarations are incorrect.d' 0he code segment is error free

1;.V./. 3ill in the blan" line identified in the VHDL code fragment below with the appropriatecommand that will assign a value of one to the variable temp.

5&HI0&0B5 test 43 test I++ICL temp/J IC05

)IC,54&++ (temp/'

V5I)L tempJ IC05)IC

+ill in the ,lan- heretemp/ K temp M 1

out K temp/CD ,54&++CD 0+0

a' temp JK 1Gb' temp JK 1c' temp JK 1.;

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cuestiones_vhdl_basico

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