“tapped” - rovira i virgili universitydeeea.urv.cat/public/propostes/pub/pdf/218pub.pdf ·...

Análisis de prototipos

“Tapped”

en lazo abierto

AUTOR: Daniel Agustín de Dios.

PONENTE: Hugo Valderrama Blavi.

FECHA: Septiembre / 2002

P.F.C: Convertidores DC/DC: Análisis de prototipos “Tapped” en lazo abierto

INDICE

1 Introducción

1.1 Objetivos y justificación del proyecto.

1.2 Introducción a los convertidores.

1.3 Análisis del proyecto.

1.4 Modelo equivalente de bobinas acopladas.

2 Memoria descriptiva.

2.1 Topologías básicas.

2.1.1 Circuitos y ecuaciones de estado.

2.1.2 Valores en régimen estacionario.

2.1.3 Modelos en pequeña señal.

2.1.4 Tabla resumen.

2.2 Topologías “ Tapped “.

2.2.1 Circuitos y ecuaciones de estado.

2.2.2 Valores en régimen estacionario.

2.2.3 Modelos en pequeña señal.

2.2.4 Tablas resumen.

2.3 Análisis dinámico de la respuesta frecuencial.

2.3.1 Introducción.

2.3.2 Dinámica comparada: Topologías elevadoras.

2.3.3 Dinámica comparada: Topologías reductoras.

3 Memoria de cálculo.

3.1 Topologías básicas: Rizados ∆∆ IL , ∆∆VC.

3.2 Topologías “ Tapped “: Rizados ∆∆ IL , ∆∆VC.

3.3 Respuesta frecuencial y temporal con Matlab.

3.3.1 Topologías elevadoras ( Boost + Tapped).

3.3.2 Topologías reductoras (Buck + Tapped).

3.3.3 Parámetros dinámicos y tabla resumen.


4 Simulación y resultados experimentales.

4.1 Topologías básicas (Pspice).

4.2 Topologías “Tapped” (Pspice).

4.3 Prototipos experimentales.

4.4 Comparación simulación-Prototipo.

4.4.1 Buck.

4.4.2 Tapped Buck 1.


4.4.4 Tapped Boost 1.

4.4.5 Tapped Boost 2.

4.4.6 Otras gráficas.

5 Conclusiones.

6 Planos y presupuestos.

6.1 Esquemáticos de los drivers.

6.2 Posibles drivers alternativos.

6.3 Presupuesto.

7 Pliego de condiciones.

Apéndide.

Anexo A.

Programas Pspice.

Programas Matlab.

Resultados Wmaple.

Anexo B.

Realización inductores acoplados.

Anexo C.

Archivos PDF.

P.F.C: Convertidores DC/DC: Análisis de prototipos “Tapped” en lazo abi erto

Página 1 de 6

1 Introducción. 1.1. Objetivos y justificación del proyecto.

El Objetivo de dicho proyecto que se va a analizar se basa en el estudio de cuatro topologías DC/DC denominados Convertidores-Tapped. Con la ayuda de los topologías básicas e ideales Buck, Boost y Buck-Boost, se van a comparar y obtener conclusiones. El proyecto consta de dos partes: la parte teórica donde el estudio se basa en simulaciones y el montage donde se comparan resultados con los teóricos.

Existen pocas aplicaciones que justifiquen el diseño y la creación de nuevos convertidores ó topologías conmutadas. Para la mayor parte de las aplicaciones ya existen topologías adecuadas suficientemente simples, incluso en la mayoría de las veces convertidores como el Buck, Boost y Buck-Boost pueden ser utilizados ventajosamente en aplicaciones concretas. Circuitos más complicados como el Forward, el Flyback o el Cuk no serían necesarios. Es cierto que el Cuk ò convertidor de topología óptima presente ventajas como ausencia de corrientes pulsantes en la entrada y en la salida, pero presenta desventajas como una dinámica más compleja y mayores pérdidas. El forward (Buck) y el flyback Buck-Boost) tienen como ventajas permitir múltiples salidas aisladas entre sí y de la entrada, pero su principal inconveniente es el complejo diseño de los transformadores. Uno de las maneras más simples de alterar, en aquellas aplicaciones en que sea preciso, las características de los convertidores elementales es el “Tappeado” del inductor presente en dichos convertidores. Entre los beneficios que pueden ser obtenidos destacan mejores propiedades de regulación cruzada, niveles mas bajos de EMI, reducción en el stress de algunos componentes, y en algunos casos la eliminación ó desplazamiento de polos del semiplano izquierdo y de ceros del semiplano derecho en las funciones de pequeña señal. De esta forma, las topologías “Tapped” pueden tener un lazo de control más estable, ó de diseño más fácil. 1.2. Introducción a los Convertidores.

En primer lugar antes de entrar en contacto con las condiciones iniciales en de las cuales se basa el presente proyecto se va a realizar una pequeña introducción de los convertidores para una mejor comprensión de dicho proyecto. Un convertidor es un sistema procesador de potencia. Controla el flujo de energía entre una fuente y una carga con la mayor eficiencia posible. Idealmente dicha eficiencia debería ser del 100%. O sea, que toda la potencia de entrada fuera igual a la potencia de salida. Pero en la práctica no es posible. Siempre aparecen pequeñas perdidas, pero aún así, la eficiencia es elevada. Lo que se intenta es que no consuma energía posible, pero sino, que ésta sea lo mínimo posible.


Página 2 de 6

En la actualidad hay una gran variedad de convertidores pero se pueden agrupar en 4 grandes grupos: • Convertidores AC/AC • Convertidores AC/DC • Convertidores DC/AC • Convertidores DC/DC El estudio en el cual se basa dicho proyecto contempla el análisis de los convertidores DC/DC y que a continuación se va a mostrar un pequeño esquema.

Fig. 1.1 Esquema de un convertidor DC- DC Como se observa en el anterior esquema, un convertidor esta basado en cinco elementos: • Fuente. • Almacenador de energía (Bobina) • Modulador de anchura de pulsos. • Filtro de salida. • Carga. En dicho proyecto no se nombra el control ya que se realiza un análisis en lazo abierto. El modulador de anchura de pulsos genera una señal de control para el interruptor del convertidor. Variando el “ Duty-Cicle “ de esa señal, se controla la cantidad de energía almacenada en la bobina y con ello se obtiene la salida deseada con la ayuda de un filtro.


Página 3 de 6

1.3 Análisis del proyecto. El Objetivo del proyecto que acontinuación se va a analizar se basa en el estudio

de 4 convertidores DC/DC denominados Convertidores-Tapped. Dichos convertidores su característica principal es que como almacenador de energía tiene dos bobinas acopladas en vez de una sola bobina. A partir de los convertidores básicos e ideales Buck, Boost y Buck-Boost, que son los más utilizados se van a comparar y obtener conclusiones. Este proyecto consta de análisis mediante modelos matriciales de ecuaciones de estado (teórico y con Wmaple32), simulaciones con Pspice, análisis dinámico en pequeña señal (teórico y con Matlab) y contrucción de prototipos en lazo abierto (con Protel). A continuación se muestran las topologías que serán anlalizadas:

TOPOLOGÍAS TOPOLOGÍAS TAPPED

BUCK(Step Down)

TAPPED-BUCK 1

BOOST(Step up)

TAPPED-BUCK 2

BUCK-BOOST

TAPPED-BOOST 1

CUK

TAPPED-BOOST 2


Página 4 de 6

Las especificaciones del presente proyecto se basan en el estudio de los convertidores utilizando los mismos elementos, pero variando su conexionado tal y como se ha mostrado en los esquemas anteriores. Los circuitos reductores, lo que se intenta realizar es una regulación de 40V a 20V, para ello con los mismos componentes lo que se hace es variar en “Duty-Cicle” o modulación de anchura de pulsos. Y los circuitos elevadores su regulación es de 20V a 40V. Los elementos utilizados son: Bobinas acopladas : L1,L2 = 333 µH Condensador : C = 83 µF. Resistencia (reductores) : R = 10 Ω Resistencia (elvadores) : R = 40 Ω


Página 5 de 6

1.4. Modelo equivalente de bobinas acopladas. Las corrientes en los inductores Tapped son discontinuas y para poder aplicar el método del promediado en el espacio de estado se necesitan variables contínuas. No se trabajará con iL1 e iL2, sino con iLm que es la corriente por la inductancia de mangetización que resulta ser contínua. Dicho inductancia de magnetización modeliza el hecho de que la Reluctancia del núcleo no es nula. i1 i2 i1 i2 + + + +

V1 V2 V1 V2

- - - -

Fig 1.2. Transformador ideal Fig 1.3. Trafo con inductacia magnetizante Por consiguiente para el análisis de los circuitos Tapped se seguirá los siguientes pasos indicados a continuación:

1º Paso Inductor del Tapped 2º Paso Bobinas acopladas

3º Paso Trafo ideal acoplado 4º Paso Trafo real acomplado con Lm

n1 : n2

n1 : n2

n1:n2 n1:n2


Página 6 de 6

La relación de dicha bobina acoplada es la mostrada a continuación: i1 i2 + +

V1 V2 - -

Fig. 1.4. Trafo con inductacia magnetizante

Donde:

⋅=

⋅=⇒=

21

12

1

2

InI

VnV

n

nn (1.1)

Por ello a continuación se realizará el estudio de los circuitos Tapped basándose en este esquema idealizado. A la hora de realizar la simulación en Pspice se ha elegido oportuno hacer dos tipos de simulaciones. Uno de ellos es con el esquema anteriormente hallado imitando el transformador con fuentes dependientes de tensión y corriente para simular las ecuaciones anteriormente mencionadas y el segundo es con bobinas acopladas (aunque por defecto su acoplamiento no puede ser 1, pero si bastante aproximado).

i1 i2

+ +

V1 V2

- -

Fig. 1.5. Modelo Pspice del Transformador con induct. magnetizante.

n1:n2


Página 1 de 56

2 Memoria descriptiva. 2.1. Topologías básicas. Antes de empezar con en análisis de los cuatro circuitos Tapped en concreto se realizará el estudio de los convertidores Buck, Boost y Buck-Boost mediante las ecuaciones de estado. Se comienza con éstos por su mayor simplicidad y para conocer con claridad la resolución de los circuitos mediante ecuaciones de estado. 2.1.1. Ciruitos y Ecuaciones de Estado. A continuación se va ha realizar el análisis promediado de las ecuaciones de estado.

Fig. 2.1 Esquema del modelo promediado de ecuaciones de estado.

MODELO PROMEDIADO

⋅+⋅=

⋅+⋅=

VgBoffXAoffX

VgBonXAonX

VgBmedXAmedX ⋅+⋅=

donde

(2.1)

)D(BoffDBoffBmed

)D(AoffDAonAmed

−⋅+⋅=−⋅+⋅=

1

1

X(t) X (t) X(t+TON) X(t+T)

t

Med

ON OFF


Página 2 de 56

Su esquema matricial sigue la ecuación que se muestra a continuación:

•

+

•

=

u

v

b

b

v

i

aa

aa

v

i g

B

c

L

A

_

c

_

L

2

1

2221

1211

44 844 76

(2.2)

cuyos elementos son:

→→

→

→

→

−

−

entrada_Tensiónv

rcondensado_el_en_Corrientev

bobina_la_en_Corrienteidt

dvv

dt

dii

g

C

L

CC

LL

Donde la matriz que depende la dinámica del sistema “Amed”, sus valores está formada por una serie de matrices que describen el convertidor cuando está en conducción o no lo está. Dicha matriz se obtiene a partir de la ecuación:

43421

oDiscontínuModo

sdis

s

offoff

s

ononmed

med

T

tA

T

tA

T

tAA

aa

aaA

3

2221

1211

⋅+⋅+⋅=

=

(2.3)

Como puede observarse cada matriz se pondera según el periodo de conducción ó “Duty cicle” cuyo valor es una fracción del periodo total de la señal. La tercera matriz “Adis” corresponde al modo discontínuo. En este análisis no se considerará este modo de conducción. Por consiguiente se analizarán las tres topologías únicamente en modo contínuo.


Página 3 de 56

Convertidor Buck A continuación se muestra una pequeña leyenda para poder entender con mayor facilidad el desarrollo que será mostrado a continuación: Ton : Interruptor en ON. Diodo en OFF. Toff : Interruptor en OFF. Diodo en ON. T3 : Interruptor y diodo en OFF.

Fig. 2.2 Esquema circuital y forma de onda de la corriente a través de la bobina.

Aon:

11

11

⋅−⋅=

⋅+⋅−=

R

v

Ci

Cdt

dv

vL

vLdt

di

cL

c

gcL

(2.4)

•

+

•

⋅−

−=

u

vL

v

i

RCC

L

v

i g

c

L

_

c

_

L

0

1

11

10

(2.5)


Página 4 de 56

Aoff:

R

viii

dt

dvCi

dt

diLvv

cLoL

cc

LcL

−=−=⋅=

⋅=−=

(2.6)

•

+

•

⋅−

−=

u

v

v

i

RCC

L

v

i g

c

L

_

c

_

L

00

11

10

(2.7)

Ahora hacemos la hipótesis CCM (trabajamos en modo contínuo), donde Ts = ton + toff y

donde s

on

T

tD = .

DL

v)D(BDBB

A)D(ADAA

goffonmed

onoffonmed

⋅=−⋅+⋅=

=−⋅+⋅=

1

1

(2.8)

Y la ecuación de estado final es:

•

+

•

⋅−

−=

u

v

L

D

v

i

RCC

L

v

i g

c

L

_

c

_

L

011

10

(2.9)


Página 5 de 56

Convertidor Boost


Aon:

CR

vc

dt

dv

R

v

dt

dvCi

L

v

dt

di

dt

diLvv

cccc

gLLgL

⋅−=⇒−=⋅=

=⇒⋅==

(2.10)

•

+

•

⋅−

=

u

vL

v

i

RCv

i g

c

L

_

c

_

L

0

11

0

00 (2.11)


Página 6 de 56

Aoff:

( )

CR

vi

Cdt

dv

R

viii

dt

dvCi

vvLdt

di

dt

diLvvv

cL

ccLoL

cc

cgLL

cgL

⋅−⋅=⇒−=−=⋅=

−⋅=⇒⋅=−=

1

1

(2.12)

•

+

•

⋅−

−=

u

vL

v

i

RCC

L

v

i g

c

L

_

c

_

L

0

1

11

10

(2.13)

Ahora hacemos la hipótesis CMM (trabajamos en modo contínuo), donde Ts = ton + toff y

donde s

on

T

tD = .

( )

( ) ( )

( )

( )

L

v)D(BDBB

CRC

DL

D

CR

D

C

DL

D

CR

D)D(ADAA

goffonmed

offonmed

=−⋅+⋅=

⋅−−

−−

=

⋅−−−

−−

+

⋅−=−⋅+⋅=

1

11

10

11

10

0

001

(2.14)


( )

( )

•

+

•

⋅−−

−−=

u

v

L

v

i

RCCD

L

D

v

i g

c

L

_

c

_

L

0

1

11

10

(2.15)


Página 7 de 56

Convertidor Buck - Boost


Aon:

CR

v

dt

dv

R

v

dt

dvCi

L

v

dt

di

dt

diLvv

ccccc

gLLgL

⋅−=⇒=⋅−=

=⇒⋅==

(2.16)

•

+

•

⋅−

=

u

vL

v

i

RCv

i g

c

L

_

c

_

L

0

11

0

00 (2.17)


Página 8 de 56

Aoff:

CR

vi

Cdt

dv

R

viii

dt

dvCi

L

v

dt

di

dt

diLvv

cL

ccLoL

cc

cLLcL

⋅−⋅=⇒−=−=⋅=

=⇒⋅==

1

(2.18)

•

+

•

⋅−

=

u

v

v

i

RCC

L

v

i g

c

L

_

c

_

L

00

11

10

(2.19)


donde s

on

T

tD = .

( )

( )

goffonmed

offonmed

vL

D)D(BDBB

CRCD

L

D

)D(ADAA

⋅=−⋅+⋅=

⋅−−

−

=−⋅+⋅=

1

11

10

1

(2.20)


( )

( )

•

+

•

⋅−−

−

=

u

v

L

D

v

i

RCCD

LD

v

i g

c

L

_

c

_

L

011

10

(2.21)


Página 9 de 56

A continuación vamos a mostrar un cuadro resumen del modelo promediado de las ecuaciones de estado:

TOPOLOGÍAS Matrices de estado

BUCK →→ Step Down

•

+

•

⋅−

−=

u

v

L

D

v

i

RCC

L

v

i g

c

L

_

c

_

L

011

10

BOOST →→ Step up

( )

( )

•

+

•

⋅−

−

−−

=

u

v

L

v

i

RCC

DL

D

v

i g

c

L

_

c

_

L

0

1

11

10

BUCK-BOOST

( )

( )

•

+

•

⋅−

−

−

=

u

v

L

D

v

i

RCC

DL

D

v

i g

c

L

_

c

_

L

011

10

Fig. 2.5 Cuadro resumen de las ecuaciones de estado. A partir de las matrices de estado halladas, se va a obtener los diferentes valores en régimen estacionario, su modelo en pequeña señal y su impedancia de salida.


Página 10 de 56

2.1.2. Valores en Régimen estacionario. Para Obtener el Régimen estacionario se realiza:

0=dT

dX

(2.22) VgBmedXssAmed ⋅+⋅=0

VgBmedAmedXss ⋅⋅−= −1

Convertidor Buck

Auss y Buss son las matrices promediadas (conocidas anteriormente por Amed y

Bmed) en régimen estacionario (ahora las llamaremos así). Y como observaremos a continuación siguen una relación matricial:

⋅

⋅−

−=⋅−=

−

−

0

1

11

10

1

1 L

RCC

LBussAussXss (2.23)

−

−=

−

−⋅=−

001

11

111

L

CR

L

C

LRC

LC

Auss (2.24)

⋅=

⋅=

⋅⋅

−

−−=

=

g

gg

vDV

vR

DIv

L

D

L

CR

L

V

IXss

00 (2.25)


Página 11 de 56

Convertidor Boost

( )

( )

⋅

⋅−−

−−=⋅−=

−

−

011

10

1

1L

v

RCC

DL

D

BussAussXssg

(2.26)

( )

( )

( )( ) ( )

( )

−−

−−⋅−

=

−−

−−⋅

−=−

01

11

01

11

1

2

21

D

LD

C

DR

L

C

DL

DRC

D

LCAuss (2.27)

( ) ( )

( )

( )

( )

−=

−⋅=

⋅

−−

−−⋅−

−=

=

D

vV

DR

vI

L

v

D

LD

C

DR

L

V

IXss

g

gg

1

1

00

1

1122

(2.28)


Página 12 de 56

Convertidor Buck–Boost

( )

( )

⋅⋅

⋅−−

−−=⋅−=

−

−

011

10

1

1 gvL

D

RCC

DL

D

BussAussXss (2.29)

( )

( )

( )( ) ( )

( )

−−

−−⋅−

=

−−

−−⋅

−=−

01

11

01

11

1

2

21

D

LD

C

DR

L

C

DL

DRC

D

LCAuss (2.30)

( ) ( )

( )

( )

( )

⋅−

=

−⋅

⋅=

⋅⋅

−−

−−⋅−

−=

=

g

gg

vD

DV

DR

vDIv

L

D

D

LD

C

DR

L

V

IXss

1

1

00

1

11 22 (2.31)


Página 13 de 56

Tabla resumen de los valores de los modelos promediados en régimen estacionario.

TOPOLOGÍA Régimen Estacionario

BUCK →→ Step down

⋅=

⋅=

⋅⋅

−

−−=

=

gC

gLg

C

L

vDV

vR

DIv

LD

L

CRL

V

IXss

00


( ) ( )

( )

( )

( )

−=

−⋅=

⋅

−−

−−⋅−

−=

=

D

vV

DR

vI

L

v

D

LD

C

DR

L

V

IXss

gC

gL

g

C

L

1

1

00

1

1122

BUCK-BOOST

( ) ( )

( )

( )

( )

⋅−

=

−⋅

⋅=

⋅⋅

−−

−−⋅−

−=

=

gC

gLg

C

L

vD

DV

DR

vDIv

L

D

D

LD

C

DR

L

V

IXss

1

1

00

1

11 22

Fig. 2.6 Cuadro resumen de los valores en régimen estacionario.


Página 14 de 56

2.1.2. Modelos en pequeña señal. Para hacer el análisis del modelo en pequeña señal añadimos una seríe de perturbaciones en pequeña señal.

A) VgBmedXAmedX ⋅+⋅= (2.32)

B)

+=

+=

+=

^

^

^

dDd

XXssX

VgVgVg

Sustituyendo B en A y despreciando los terminos que son productos de perturbaciones por perturbaciones por ser valores sumamente pequeños.

[ ] [ ] ^^^dVgBoffBonXssAoffAonVgBmedXAmedX ⋅⋅−+⋅−+⋅+⋅=

Por tanto se realiza un análisis por superposicion hanciendo ^d igual a cero y

^Vg también.


Página 15 de 56

Convertidor Buck

( )

BussVg

Bussedonde

)s(gVBusse)s(XAusss

D)s(Vg

)s(VGs

__

__

_

⋅=

⋅=⋅−

=

=

1

1

0

( ) )s(gVBusseAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

( ) ( )

−+⋅

++

=

=

−+⋅

−−+

=−⇒

⋅+−

=− −

sC

LRCs

LCRCs

s

sC

LRCs

LCRC

ss

Ausss

CRs

C

Ls

Ausss

1

11

11

1

11

11

111

1

1

2

2

1

:Finalmente

)s(gV

L

D

LCRCs

s

s

LCRC

ssC

LCRC

ssL

LCRC

ss

RCs

)s(V

)s(I _

_

_

⋅

⋅

++

++⋅

++⋅

−

++

+

=

0111

11

1

1

22

22

LCRC

ss

RCs

L

D

)s(gV

)s(I

LCRC

ss

LC

D

)s(gV

)s(V

_

_

_

_

1

1

11

2

2

++

+⋅=

++

⋅=

(2.33)


Página 16 de 56

( )

( )

⋅=−+⋅−=

⋅=⋅−

=

=

0

12121

1

0

00

VgLssBssBXssAAKdonde

)s(UK)s(XAusss

gV)s(U

)s(VGs

__

__

_

44 344 21

( ) )s(UKAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

( ) ( )

−+⋅

++

=

=

−+⋅

−−+

=−⇒

⋅+−

=− −

sC

LRCs

LCRCs

s

sC

LRCs

LCRCs

s

Ausss

CRs

C

Ls

Ausss

1

11

11

1

11

11

111

1

1

2

2

1

:Finalmente

)s(U

L

Vg

LCRCs

s

s

LCRC

ssC

LCRC

ssL

LCRC

ss

RCs

)s(V

)s(I _

_

_

⋅

⋅

++

++⋅

++⋅

−

++

+

=

0111

11

1

1

22

22

LCRC

ss

RCs

LD

Vo

LCRC

ss

RCs

L

Vg

)s(U

)s(I

LCRC

ssLCD

Vo

LCRC

ssLC

Vg

)s(U

)s(V

DViVo_

_

DViVo_

_

1

11

1

1

111

11

22

22

++

+⋅⋅ →

++

+⋅=

++⋅⋅ →

++⋅=

⋅=

⋅=

(2.34)


Página 17 de 56

Convertidor Boost

( )

BussVg

Bussedonde

)s(gVBusse)s(XAusss

D)s(Vg

)s(VGs

__

__

_

⋅=

⋅=⋅−

=

=

1

1

0

( ) )s(gVBusseAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

( )( )

( ) ( )( )

( )

( )

( )

( )

( )

−

−−+

⋅

−++

=

=

−

−−+⋅

−−−+

=−⇒

+−−

−

=− −

sC

DL

D

RCs

LCD

RCs

s

sC

DL

DRC

s

LC

D

RC

ss

Ausss

RCs

C

DL

Ds

Ausss

1

11

1

1

1

11

1

11

11

1

1

22

22

1

( )

( )( )

:Finalmente

)s(gVL

LC

D

RC

ss

C

DLC

D

RC

ss

RCs

)s(V

)s(I _

_

_

⋅

⋅

−++

⋅−

−++

+

=

1

1

11

1

1

22

22

( )( )

( )LC

D

RC

ss

RCs

L)s(gV

)s(I

LC

D

RC

ss

LC

D

)s(gV

)s(V

_

_

_

_

22

22

1

11

1

11

−++

+⋅=

−++

⋅−

=

(2.35)


Página 18 de 56

( )

( ) ( )

( )

⋅−⋅

⋅−=⋅

−=−+⋅−=

⋅=⋅−

=

=

=CDR

VgLD

Vg

Xss

C

LssBssBXssAAKdonde

)s(UK)s(XAusss

)s(gV)s(U

)s(VGs

ssBssB

__

__

_

221

1

1

01

10

2121

1

0

43421

( ) )s(UKAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

( )( )

( ) ( )( )

( )

( )

( )

( )

( )

−

−−+

⋅

−++

=

=

−

−−+⋅

−−−+

=−⇒

+−−

−

=− −

sC

DL

D

RCs

LCD

RCs

s

sC

DL

DRC

s

LC

D

RC

ss

Ausss

RCs

C

DL

Ds

Ausss

1

11

1

1

1

11

1

11

11

1

1

22

22

1

( )( )

( )

( )( ) ( )

( )

( )

:Finalmente

)s(U

DRC

Vg

LD

Vg

LC

D

RC

ss

s

LC

D

RC

ss

C

DLC

D

RC

ss

LD

LC

D

RC

ss

RCs

)s(V

)s(I _

_

_

⋅

−⋅−

⋅−

⋅

−++

−++

⋅−

−++

⋅−−−++

+

=

2

22

22

22

22

1

1

11

11

1

11

1

1

( ) ( )

( ) ( )

+⋅

−++

⋅⋅−

=

−−⋅

−++⋅=

RCs

LC

D

RC

ss

LD

Vg

)s(U

)s(I

DRC

s

LC

LC

D

RC

ss

Vg

)s(U

)s(V

_

_

_

_

2

1

11

1

1

1

1

22

222

(2.36)


Página 19 de 56

Convertidor Buck–Boost

( )

BussVg

Bussedonde

)s(gVBusse)s(XAusss

D)s(Vg

)s(VGs

__

__

_

⋅=

⋅=⋅−

=

=

1

1

0

( ) )s(gVBusseAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

( )( )

( ) ( )( )

( )

( )

−

−+⋅

−−+

=−⇒

+−−

−−=− −

sC

DL

DRC

s

LC

D

RC

ss

Ausss

RCs

C

DL

Ds

Ausss1

11

1

11

11

1

12

2

1

( )

( )( )

:Finalmente

)s(gV

LD

LC

D

RC

ss

C

DLC

D

RC

ss

RCs

)s(V

)s(I _

_

_

⋅

⋅

−−+

⋅−

−−+

+

=

01

11

1

1

22

22

( )( )

( )LC

D

RC

ss

RCs

L

D

)s(gV

)s(I

LC

D

RC

ss

LC

DD

)s(gV

)s(V

_

_

_

_

22

22

1

1

1

11

−++

+⋅=

−−+

⋅⋅−

=

(2.37)


Página 20 de 56

( )

( ) ( )( )

( )

−⋅⋅

−

+−⋅−

=

+⋅

−−

−=−+⋅−=

⋅=⋅−

=

=

DCR

VgDLDL

DVg

LXss

C

DLssBssBXssAAKdonde

)s(UK)s(XAusss

gV)s(U

)s(VGs

__

__

_

1

11

0

1

01

10

2121

1

0

( ) )s(UKAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

( )( )

( )

( )( ) ( )

( )

( )

:Finalmente

)s(U

DRC

VgD

LLD

DVg

LC

D

RC

ss

s

LC

D

RC

ss

C

DLC

D

RC

ss

LD

LC

D

RC

ss

RCs

)s(V

)s(I _

_

_

⋅

−⋅⋅

−

+⋅−

⋅−

⋅

−−+

−−+

⋅−

−−+

⋅−−−+

+

=

1

11

11

11

1

11

1

1

22

22

22

22

( )( )

( )

( )( )

( )

+−

−

−++⋅

−−+

⋅−=

−

+⋅

−−⋅

−−+⋅−=

Vg

CRs

D

DCRsD

LC

D

RC

ss

RLC

Vg

)s(gU

)s(I

DRC

Ds

VgLC

D

LC

D

LC

D

RC

ss

Vg

)s(U

)s(V

_

_

_

_

11

11

1

1

11

1

1

22

22

(2.38)


Página 21 de 56

2.1.4. Tabla resumen. Mostramos un cuadro resumen donde se observarán las funciones en el modelo de pequeña seañal de cada convertidor para que se observen con mayor facilidad:

TOPOLOGÍAS Pequeña Señal 0=

−D Pequeña señal 0=

−

gV

BUCK →→ Step down

LCRC

ss

RCs

LD

)s(gV

)s(I

LCRCs

sLC

D

)s(gV

)s(V

_

_

_

_

1

1

11

2

2

++

+⋅=

++

⋅=

LCRC

ss

RCs

LD

Vo

LCRC

ss

RCs

L

Vg

)s(U

)s(I

LCRC

ssLCD

Vo

LCRC

ssLC

Vg

)s(U

)s(V

DViVo_

_

DViVo_

_

1

11

1

1

111

11

22

22

++

+⋅⋅ →

++

+⋅=

++⋅⋅ →

++⋅=

⋅=

⋅=


( )

( )

( )LC

DRCs

s

RCs

L)s(gV

)s(I

LC

D

RC

ss

LC

D

)s(gV

)s(V

_

_

_

_

22

22

1

11

1

11

−++

+⋅=

−++

⋅−=

( ) ( )

( ) ( )

+⋅

−++

⋅⋅−

=

−−⋅

−++

⋅=

RCs

LC

D

RC

ss

LD

Vg

)s(U

)s(I

DRC

s

LC

LC

D

RC

ss

Vg

)s(U

)s(V

_

_

_

_

2

1

1

1

1

1

1

1

22

222

BUCK-BOOST

( )

( )

( )LC

D

RC

ss

RCs

L

D

)s(gV

)s(I

LC

D

RC

ss

LC

DD

)s(gV

)s(V

_

_

_

_

22

22

1

1

1

11

−++

+⋅=

−−+

⋅⋅−=

( )( )

( )

( )( )

( )

+−

−

−++⋅

−−+

⋅−=

−

+⋅

−−⋅

−−+

⋅−=

Vg

CRs

D

DCRsD

LC

D

RC

ss

RLC

Vg

)s(U

)s(I

DRC

Ds

VgLC

D

LC

D

LC

D

RC

ss

Vg

)s(U

)s(V

_

_

_

_

1

1

11

1

1

11

1

1

22

22

Fig. 2.7 Cuadro resumen de las topologías en basado en el modelo de pequeña señal.

Mediante un programa informático de matemáticas comprobamos que los resultados anteriores son correctos y además obtendremos el valor de las impedancias de salida respecto de cada tipo de convertidor. En el anexo podremos comprobar directamente los resultados del programa “Maple V Release 4”. A continuación mostramos un cuadro completo de los resultados mas interesantes del método de las matrices de estado que hemos obtenido anteriormente.


Página 22 de 56

TOPOLOGÍAS Rég. Estac. Pequeña señal ( 0=−D ) Pequeña señal ( 0=

−gV )

BUCK (Step Down)

⋅=

⋅=

gC

gL

vDV

vR

DI

LCRCs

s

RCs

LD

)s(gV

)s(I

LCRCs

sLCD

)s(gV

)s(V

_

_

_

_

1

1

11

2

2

++

+⋅=

++

⋅=

LCRC

ss

RCs

LD

Vo

LCRC

ss

RCs

L

Vg

)s(U

)s(I

LCRC

ssLCD

Vo

LCRC

ssLC

Vg

)s(U

)s(V

DViVo_

_

DViVo_

_

1

11

1

1

111

11

22

22

++

+⋅⋅ →

++

+⋅=

++⋅⋅ →

++⋅=

⋅=

⋅=

BOOST (Step up)

( )

( )

−=

−⋅=

D

vV

DR

vI

gC

gL

1

1 2

( )( )

( )LC

DRCs

s

RCs

L)s(gV

)s(I

LCD

RCs

sLC

D

)s(gV

)s(V

_

_

_

_

22

22

1

11

1

11

−++

+⋅=

−++

⋅−=

( ) ( )

( ) ( )

+⋅

−++⋅

⋅−=

−−⋅

−++⋅=

RCs

LC

D

RC

ss

LD

Vg

)s(U

)s(I

DRC

s

LC

LC

D

RC

ss

Vg

)s(U

)s(V

_

_

_

_

2

1

11

1

1

1

1

22

222

BUCK-BOOST

( )

( )

⋅−

=

−⋅

⋅=

gC

gL

vD

DV

DR

vDI

1

1 2

( )( )

( )LC

D

RC

ss

RCs

L

D

)s(gV

)s(I

LCD

RCs

sLC

DD

)s(gV

)s(V

_

_

_

_

22

22

1

1

1

11

−++

+⋅=

−−+

⋅⋅−

=

( )( )

( )

( )( )

( )

+−

−

−++⋅−−+

⋅−=

−

+⋅

−−⋅−−+

⋅−=

Vg

CRs

D

DCRsD

LC

D

RC

ss

RLC

Vg

)s(U

)s(I

DRC

Ds

VgLC

D

LC

D

LC

D

RC

ss

Vg

)s(U

)s(V

_

_

_

_

11

11

1

1

11

1

1

22

22


Página 23 de 56

Tras el estudio de los convertidores básicos, y mediante el modelo promediado de ecuaciones de estado, ahora se puede realizar el estudio de los convertidores en el que se basa este proyecto; los convertidores de bobina partida o como más comunmente se conocen los denominados “Tapped”.


Página 24 de 56

2.2. Topologías “ Tapped “.

Vamos a obtener la solución de estos cuatro tipos de convertidores mediante las ecuaciones de estado. 2.2.1. Circuitos y Ecuaciones de Estado. Su esquema matricial sigue la ecuación que a continuación es mostrada:

•

+

•

=

u

v

b

b

v

i

aa

aa

v

i g

B

c

L

A

_

c

_

L

2

1

2221

1211

44 844 76

(2.39)

cuyos elementos son:

entrada_Tensiónv

rcondensado_el_en_Corrientev

bobina_la_en_Corrienteidt

dvv

dt

dii

g

C

L

CC

LL

→→→

→

→

−

−

Y como anteriormente se ha visto, dependiendo del Duty Cicle se obtendrá la matriz “Amed” de la cual depende la dinámica del sistema:

43421

oDiscontínuModo

sdis

s

offoff

s

ononmed

med

T

tA

T

tA

T

tAA

aa

aaA

3

2221

1211

⋅+⋅+⋅=

=

(2.40)

En los modelos “Tapped”, como ya se había comentado anteriormente se analizarán las topologías únicamente en modo cointínuo.


Página 25 de 56

Convertidor Tapped - Buck 1

ON :

OFF :

Fig. 2.8 Esquema circuital y forma de onda de la corriente.

Aon:

−=⋅⇒+=

⋅=−=⇒=−−

R

vi

dt

dvCiii

dt

diLvvvvvv

CL

CRCL

LCgLCLg 0

(2.41)

•

+

•

⋅−

−=

u

vL

v

i

RCC

L

v

i g

c

L

_

c

_

L

0

1

11

10

(2.42)

≡


Página 26 de 56

Aoff:

( )

−+

=⋅⇒+⋅=+

+=

⋅+=+

−==⇒=−−−⇒=−−−

R

v

n

i

dt

dvC

R

v

dt

dvC

n

i

iii

ini

n

v

dt

diLvvvnvvvv

CLCCCL

RCq

qL

CLLCLLcL

11

11

002

(2.43)

( )

( )

•

+

•

⋅−

+⋅

+⋅−

=

u

v

v

i

RCnC

nL

v

i g

c

L

_

c

_

L

00

11

11

10

(2.44)


donde s

on

T

tD = .

DL

v)D(BDBB

)D(ADAA

goffonmed

offonmed

⋅=−⋅+⋅=

−⋅+⋅=

1

1

(2.45)


( ) ( )( )

( ) ( )( )

•

+

•

⋅−

+−++

+⋅−−+−

=

u

v

L

D

v

i

RCnC

DnD

nL

DnD

v

i g

c

L

_

c

_

L

01

111

1

110

(2.46)


Página 27 de 56

Convertidor Tapped – Buck 2

ON :

OFF:

Fig. 2.9 Esquema cirucital y forma de onda de la corriente.

( )

=−=

=+⋅+−==−−

=−−−

tdqi

dqL

CLd

dLtg

iiii

iini

vnvv

vvvv

01

0

0

Aon: vt=0 ; id=0

( )( )

( )( ) ( )

−+

=⇒+=+

+=+=

+=

=

⋅+=

⋅+−

=⇒+−

=⇒=−−−

CR

v

Cn

i

dt

dv

R

v

dt

dvC

n

i

R

v

dt

dvCiii

ni

iii

ini

Ln

vv

dtdi

n

vvvvnvvv

CLCCCL

CCRCq

Li

qi

qL

CgLCgLCLLg

111

1

110

(2.47)

( )

( )

( )

•

+⋅+

•

⋅−

⋅+

⋅+−

=

u

vnL

v

i

RCCn

Ln

v

i g

c

L

_

c

_

L

01

1

111

11

0 (2.48)

≡


Página 28 de 56

Aoff: vt=0 ; id=0

⋅−

⋅=⇒−=⋅=

−=⋅=⇒=−−

RC

v

nC

i

dt

dv

R

v

n

i

dt

dvCi

n

v

dt

diLvvnv

cLCcLcc

CLLCL 00

(2.49)

•

+

•

⋅−

⋅

⋅−

=

u

v

v

i

RCnC

nL

v

i g

c

L

_

c

_

L

00

11

10

(2.50)


donde s

on

T

tD = .

)D(BDBB

)D(ADAA

offonmed

offonmed

−⋅+⋅=

−⋅+⋅=

1

1

(2.51)


( ) ( )( )

( ) ( )( )

( )

•

⋅++

•

⋅−

++⋅−+

⋅+⋅+⋅−−−

=

u

v

Ln

D

v

i

RCnnCnDDn

nnL

nDDn

v

i g

c

L

_

c

_

L

0

11

111

111

0

(2.52)


Página 29 de 56

Convertidor Tapped - Boost 1

ON :

OFF :

Fig. 2.10 Esquema cirucuital y forma de onda de la corriente.

Aon:

CR

vc

dt

dv

R

v

dt

dvCi

L

v

dt

di

dt

diLvv

cccc

gLLgL

⋅−=⇒−=⋅=

=⇒⋅==

(2.53)

•

+

•

⋅−

=

u

vL

v

i

RCv

i g

c

L_

c

_

L

0

11

0

00 (2.54)

≡


Página 30 de 56

Aoff:

( )( ) ( ) ( ) ( )

−+

=⇒−+

=⇒

++=

+=⋅+=

⋅+−

=⇒+−

==⇒−=−

CR

v

nC

i

dt

dv

R

v

n

ii

R

vini

iii

ini

Ln

vv

dt

di

n

vv

dt

diLvnvvvv

CLCCLC

CCL

RCd

dL

CgLCgLLLCLg

111

1

11 (2.55)

( )

( )

( )

•

⋅++

•

⋅−

+⋅

⋅+−

=

u

vLn

v

i

RCnC

Ln

v

i g

c

L

_

c

_

L

011

11

111

0 (2.56)


donde s

on

T

tD = .

)D(BDBB

)D(ADAA

offonmed

offonmed

−⋅+⋅=

−⋅+⋅=

1

1

(2.57)


( )( )

( )( )

( )

•

⋅+

++

•

⋅−

+⋅−

⋅+−−

=

u

v

Ln

nD

v

i

RCnCD

Ln

D

v

i g

c

L

_

c

_

L

0

11

11

1

11

0

(2.58)


Página 31 de 56

Convertidor Tapped – Boost 2 ON :

OFF :

Fig. 2.11 Esquema circuital y forma de onda de la corriente.

Aon:

( ) ( )

⋅−=⇒−=⋅=

+⋅=⇒⋅=⇒+=⇒=−−

CR

v

dt

dv

R

v

dt

dvCi

'nL

v

dt

di

dt

diLvnvvvvv

Ccccc

gLLLLgLg 1

102

(2.59)

≡


Página 32 de 56

( )

•

+⋅+

•

⋅−

=

u

v'nL

v

i

RCv

i g

c

L

_

c

_

L

01

1

10

00 (2.60)

Aoff:

−=⇒−=⇒

+=

−=⇒−==⇒=−−

CR

v

C

i

dt

dv

R

vii

R

vii

L

vv

dt

divv

dt

diLvvvv

CLCCLC

CCL

CgLCg

LLCLg 0

(2.61)

•

+

•

⋅−

−=

u

vL

v

i

RCC

L

v

i g

c

L

_

c

_

L

0

1

11

10

(2.62)


donde s

on

T

tD = .

)D(BDBB

)D(ADAA

offonmed

offonmed

−⋅+⋅=

−⋅+⋅=

1

1

(2.63)


( )

( )

( )( )

•

⋅+

+−+

•

⋅−−

−−=

u

v

L'nD'n

v

i

RCCD

LD

v

i g

c

L

_

c

_

L

01

11

11

10

(2.64)


Página 33 de 56

Se observan los valores obtendios de las diferentes topologías Tapped que están recogidas en la siguiente tabla de matrices de estado.

TOPOLOGÍAS Matrices de estado TAPPED-BUCK 1

2

1

L

L

N

Non ==

( ) ( )( )

( ) ( )( )

•

+

•

⋅−

+−++

+⋅−−+−

=

u

v

LD

v

i

RCnCDnD

nLDnD

v

i g

c

L

_

c

_

L

01111

1110

TAPPED-BUCK 2

21

L

L

N

Non ==

( ) ( )( )

( ) ( )( )

( )

•

⋅++

•

⋅−

++⋅−+

⋅+⋅+⋅−−−

=

u

v

Ln

D

v

i

RCnnC

nDDn

nnL

nDDn

v

i g

c

L

_

c

_

L

0

11

111

111

0

TAPPED-BOOST 1

21

L

L

N

Non ==

( )( )

( )( )

( )

•

⋅+

++

•

⋅−

+⋅−

⋅+−−

=

u

v

LnnD

v

i

RCnCD

LnD

v

i g

c

L

_

c

_

L

01

1

11

11

10

TAPPED-BOOST 2

1nn

LLL

NNo

'n21

1

T +=

+==

( )

( )

( )( )

•

⋅+

+−+

•

⋅−

−

−−

=

u

v

L'n

D'n

v

i

RCC

DL

D

v

i g

c

L

_

c

_

L

0

111

11

10

Fig. 2.12 Cuadro resumen de las ecuaciones de estado.

A partir de las matrices de estado se da paso a obtener los diferentes valores en régimen estacionario, su modelo en pequeña señal y su impedancia de salida:


Página 34 de 56

2.2.2. Valores en Régimen estacionario.

TOPOLOGÍAS Régimen Estacionario TAPPED-BUCK 1

2

1

L

L

N

Non ==

( )( )

( )( ) gC

gL

vDn

DnV

vDnR

DnI

⋅+

+=

⋅+

+=

11

1

12

2

TAPPED-BUCK 2

2

1

L

L

N

Non ==

( )( )

( ) gC

gL

vDn

nDV

vDnR

DnnI

⋅−+

=

⋅−+

+=

1

1

12

2

TAPPED-BOOST 1

2

1

L

L

N

Non ==

( )( )

( )

( )( ) gC

gL

vD

nDV

vDR

nDnI

⋅−

+=

⋅−

++=

11

1

112

TAPPED-BOOST 2

1nn

LL

L

NNo

'n21

1

T +=

+==

[ ]( )

( ) ( )

[ ]( )( )( ) gC

gL

v'nD

D'nV

v'nDR

D'nI

⋅+−+−=

⋅+−

+−=

1111

11

112



Página 35 de 56

2.2.3. Modelos en pequeña señal.

Convertidor Tapped - Boost 1

( )

BussVg

Bussedonde

)s(gVBusse)s(XAusss

D)s(Vg

)s(VGs

__

__

_

⋅=

⋅=⋅−

=

=

1

1

0

( ) )s(gVBusseAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

Finalmente:

( ) ( )( ) ( ) ( )

( ) ( ) ( )( ) ( ) ( )2222

2222

111

111

111

11

TTTTTT

TTT_

_

TTTTTT

TTT_

_

DRnsLnCRLs

nDnCsR

)s(gV

)s(I

DRnsLnCRLs

nDRD

)s(gV

)s(V

−++⋅++⋅

+⋅+⋅+=

−++⋅++⋅

+⋅⋅−=

(2.65)


Página 36 de 56

( )

( )

⋅=−+⋅−=

⋅=⋅−

=

=

0

12121

1

0

00


)s(UK)s(XAusss

gV)s(U

)s(VGs

__

__

_

44 344 21

( ) )s(UKAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

Finalmete :

( ) ( )[ ]( ) ( )( ) ( ) ( )( ) ( )

( ) ( ) ( )( ) ( ) ( )( ) ( )TTTTTTT

gTTT_

_

TTTTTTT

gTTT_

_

DDRnsLnCRLs

VCsRnDn

)s(U

)s(I

DDRnsLnCRLs

VnDnnsLDR

)s(U

)s(V

−⋅−++⋅++⋅

⋅+⋅+⋅+=

−⋅−++⋅++⋅

⋅+⋅++−−=

1111

211

1111

1111

2222

2

22222

22

(2.66)


Página 37 de 56

Convertidor Tapped – Boost 2

( )

BussVg

Bussedonde

)s(gVBusse)s(XAusss

D)s(Vg

)s(VGs

__

__

_

⋅=

⋅=⋅−

=

=

1

1

0

( ) )s(gVBusseAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

Finalmente:

( ) ( )( )( ) ( ) ( ) ( )

( ) ( )( )( ) ( ) ( ) ( )1111

111

1111

111

22

22

+⋅−++⋅++⋅

+−⋅+=

+⋅−++⋅++⋅

+−⋅⋅−=

'nDR'nsL'nCRLs

D'nCsR

)s(gV

)s(I

'nDR'nsL'nCRLs

D'nRD

)s(gV

)s(V

TTTTTT

TTT_

_

TTTTTT

TTT_

_

(2.67)


Página 38 de 56

( )

( )

⋅=−+⋅−=

⋅=⋅−

=

=

0

12121

1

0

00


)s(UK)s(XAusss

gV)s(U

)s(VGs

__

__

_

44 344 21

( ) )s(UKAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

Finalmente :

( )[ ] ( )( )( )( ) ( ) ( )

[ ] ( )( )( )( ) ( ) ( )111

112

111

111

22

222

2

+⋅−⋅−++

⋅+−⋅+=

+⋅−⋅−++

⋅+−⋅−−=

'nDDRsLCRLs

VD'nCsR

)s(U

)s(I

'nDDRsLCRLs

VD'nsLDR

)s(U

)s(V

TTTTTTT

gTTT_

_

TTTTTTT

gTTT_

_

(2.68)


Página 39 de 56

Convertidor Tapped-Buck 1

( )

BussVg

Bussedonde

)s(gVBusse)s(XAusss

D)s(Vg

)s(VGs

__

__

_

⋅=

⋅=⋅−

=

=

1

1

0

( ) )s(gVBusseAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

Finalmente:

( ) ( )( ) ( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( ) ( )[ ]2222

2

2222

1111

11

1111

11

TTTTTTT

TTT_

_

TTTTTTT

TTT_

_

DnDRnsLnCRLs

nRsCD

)s(gV

)s(I

DnDRnsLnCRLs

nnDDR

)s(gV

)s(V

−++⋅++⋅++⋅

+⋅+=

−++⋅++⋅++⋅

+⋅+⋅⋅=

(2.69)


Página 40 de 56

( )

( )

⋅=−+⋅−=

⋅=⋅−

=

=

0

12121

1

0

00


)s(UK)s(XAusss

gV)s(U

)s(VGs

__

__

_

44 344 21

( ) )s(UKAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

Finalmete :

( ) ( )( ) ( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( ) ( )[ ]2222

2

2222

1111

11

1111

11

TTTTTTT

gTT_

_

TTTTTTT

gTT_

_

DnDRnsLnCRLs

VnRsC

)s(U

)s(I

DnDRnsLnCRLs

VnnDR

)s(U

)s(V

−++⋅++⋅++⋅

⋅+⋅+=

−++⋅++⋅++⋅

⋅+⋅+=

(2.70)


Página 41 de 56

Convertidor Tapped – Buck 2

( )

BussVg

Bussedonde

)s(gVBusse)s(XAusss

D)s(Vg

)s(VGs

__

__

_

⋅=

⋅=⋅−

=

=

1

1

0

( ) )s(gVBusseAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

Finalmente:

( )( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( )[ ]222222

2

222222

111

11

111

1

TTTTTT

TTT_

_

TTTTTT

TTT_

_

DnRnnsLnnCRLs

DnnRsC

)s(gV

)s(I

DnRnnsLnnCRLs

DnDRn

)s(gV

)s(V

−+⋅++⋅⋅++⋅⋅

⋅⋅+⋅+=

−+⋅++⋅⋅++⋅⋅

−+⋅⋅⋅=

(2.71)


Página 42 de 56

( )

( )

⋅=−+⋅−=

⋅=⋅−

=

=

0

12121

1

0

00


)s(UK)s(XAusss

gV)s(U

)s(VGs

__

__

_

44 344 21

( ) )s(UKAusss

)s(V

)s(I)s(X

_

_

__

⋅⋅−=

= −11

Finalmente :

( )( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( )[ ]222222

2

222222

111

11

111

1

TTTTTT

gTT_

_

TTTTTT

gTT_

_

DnRnnsLnnCRLs

VnnRsC

)s(U

)s(I

DnRnnsLnnCRLs

VRnDn

)s(U

)s(V

−+⋅++⋅⋅++⋅⋅

⋅⋅+⋅+=

−+⋅++⋅⋅++⋅⋅

⋅⋅⋅−+=

(2.72)


Página 43 de 56



−

gV

TAPPED-BUCK 1

( ) ( )( ) ( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( ) ( )[ ]2222

2

2222

1111

11

1111

11

TTTTTTT

TTT_

_

TTTTTTT

TTT_

_

DnDRnsLnCRLs

nRsCD

)s(gV

)s(I

DnDRnsLnCRLs

nnDDR

)s(gV

)s(V

−++⋅++⋅++⋅

+⋅+=

−++⋅++⋅++⋅

+⋅+⋅⋅=

( ) ( )( ) ( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( ) ( )[ ]2222

2

2222

1111

11

1111

11

TTTTTTT

gTT_

_

TTTTTTT

gTT

_

_

DnDRnsLnCRLs

VnRsC

)s(U

)s(I

DnDRnsLnCRLs

VnnDR

)s(U

)s(V

−++⋅++⋅++⋅

⋅+⋅+=

−++⋅++⋅++⋅

⋅+⋅+=

TAPPED-BUCK 2

( )( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( )[ ]222222

2

222222

111

11

111

1

TTTTTT

TTT_

_

TTTTTT

TTT_

_

DnRnnsLnnCRLs

DnnRsC

)s(gV

)s(I

DnRnnsLnnCRLs

DnDRn

)s(gV

)s(V

−+⋅++⋅⋅++⋅⋅

⋅⋅+⋅+=

−+⋅++⋅⋅++⋅⋅

−+⋅⋅⋅=

( )( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( )[ ]222222

2

222222

111

11

111

1

TTTTTT

gTT

_

TTTTTT

gTT

_

_

DnRnnsLnnCRLs

VnnRsC

)s(U

)s(I

DnRnnsLnnCRLs

VRnDn

)s(U

)s(V

−+⋅++⋅⋅++⋅⋅

⋅⋅+⋅+=

−+⋅++⋅⋅++⋅⋅

⋅⋅⋅−+=

−

TAPPED-BOOST 1

( ) ( )( ) ( ) ( )

( ) ( ) ( )( ) ( ) ( )2222

2222

111

111

111

11

TTTTTT

TTT_

_

TTTTTT

TTT_

_

DRnsLnCRLs

nDnCsR

)s(gV

)s(I

DRnsLnCRLs

nDRD

)s(gV

)s(V

−++⋅++⋅

+⋅+⋅+=

−++⋅++⋅

+⋅⋅−=

( ) ( )[ ]( ) ( )( ) ( ) ( )( ) ( )

( ) ( ) ( )( ) ( ) ( )( ) ( )TTTTTTT

gTTT_

_

TTTTTTT

gTTT

_

_

DDRnsLnCRLs

VCsRnDn

)s(U

)s(I

DDRnsLnCRLs

VnDnnsLDR

)s(U

)s(V

−⋅−++⋅++⋅

⋅+⋅+⋅+=

−⋅−++⋅++⋅

⋅+⋅++−−=

1111

211

1111

1111

2222

2

22222

22

TAPPED-BOOST 2

( ) ( )( )( ) ( ) ( ) ( )

( ) ( )( )( ) ( ) ( ) ( )1111

111

1111

111

22

22

+⋅−++⋅++⋅

+−⋅+=

+⋅−++⋅++⋅

+−⋅⋅−=

'nDR'nsL'nCRLs

D'nCsR

)s(gV

)s(I

'nDR'nsL'nCRLs

D'nRD

)s(gV

)s(V

TTTTTT

TTT_

_

TTTTTT

TTT_

_

( )[ ] ( )( )( )( ) ( ) ( )

[ ] ( )( )( )( ) ( ) ( )111

112

111

111

22

222

2

+⋅−⋅−++

⋅+−⋅+=

+⋅−⋅−++

⋅+−⋅−−=

'nDDRsLCRLs

VD'nCsR

)s(U

)s(I

'nDDRsLCRLs

VD'nsLDR

)s(U

)s(V

TTTTTTT

gTTT

_

_

TTTTTTT

gTTT

_

_


Página 44 de 56

2.2.4 Tablas resumen.

TOPOLOGÍAS Régimen Estacionario TAPPED-BUCK 1

2

1

L

L

N

Non ==

( )( )

( )( ) gC

gL

vDn

DnV

vDnR

DnI

⋅+

+=

⋅+

+=

11

1

12

2

TAPPED-BUCK 2

2

1

L

L

N

Non ==

( )( )

( ) gC

gL

vDn

nDV

vDnR

DnnI

⋅−+

=

⋅−+

+=

1

1

12

2

TAPPED-BOOST 1

2

1

L

L

N

Non ==

( )( )

( )

( )( ) gC

gL

vD

nDV

vDR

nDnI

⋅−

+=

⋅−

++=

11

1

112

TAPPED-BOOST 2

21

1

LL

L

N

No'n

T +==

[ ]( )

( ) ( )

[ ]( )( )( ) gC

gL

v'nD

D'nV

v'nDR

D'nI

⋅+−+−=

⋅+−

+−=

1111

11

112




−

gV

TAPPED-BUCK 1

( ) ( )( ) ( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( ) ( )[ ]2222

2

2222

1111

11

1111

11

TTTTTTT

TTT_

_

TTTTTTT

TTT_

_

DnDRnsLnCRLs

nRsCD

)s(gV

)s(I

DnDRnsLnCRLs

nnDDR

)s(gV

)s(V

−++⋅++⋅++⋅

+⋅+=

−++⋅++⋅++⋅

+⋅+⋅⋅=

( ) ( )( ) ( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( ) ( )[ ]2222

2

2222

1111

11

1111

11

TTTTTTT

gTT_

_

TTTTTTT

gTT

_

_

DnDRnsLnCRLs

VnRsC

)s(U

)s(I

DnDRnsLnCRLs

VnnDR

)s(U

)s(V

−++⋅++⋅++⋅

⋅+⋅+=

−++⋅++⋅++⋅

⋅+⋅+=

TAPPED-BUCK 2

( )( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( )[ ]222222

2

222222

111

11

111

1

TTTTTT

TTT_

_

TTTTTT

TTT_

_

DnRnnsLnnCRLs

DnnRsC

)s(gV

)s(I

DnRnnsLnnCRLs

DnDRn

)s(gV

)s(V

−+⋅++⋅⋅++⋅⋅

⋅⋅+⋅+=

−+⋅++⋅⋅++⋅⋅

−+⋅⋅⋅=

( )( ) ( ) ( )[ ]

( ) ( )( ) ( ) ( )[ ]222222

2

222222

111

11

111

1

TTTTTT

gTT

_

TTTTTT

gTT

_

_

DnRnnsLnnCRLs

VnnRsC

)s(U

)s(I

DnRnnsLnnCRLs

VRnDn

)s(U

)s(V

−+⋅++⋅⋅++⋅⋅

⋅⋅+⋅+=

−+⋅++⋅⋅++⋅⋅

⋅⋅⋅−+=

−

TAPPED-BOOST 1

( ) ( )( ) ( ) ( )

( ) ( ) ( )( ) ( ) ( )2222

2222

111

111

111

11

TTTTTT

TTT_

_

TTTTTT

TTT_

_

DRnsLnCRLs

nDnCsR

)s(gV

)s(I

DRnsLnCRLs

nDRD

)s(gV

)s(V

−++⋅++⋅

+⋅+⋅+=

−++⋅++⋅

+⋅⋅−=

( ) ( )[ ]( ) ( )( ) ( ) ( )( ) ( )

( ) ( ) ( )( ) ( ) ( )( ) ( )TTTTTTT

gTTT_

_

TTTTTTT

gTTT

_

_

DDRnsLnCRLs

VCsRnDn

)s(U

)s(I

DDRnsLnCRLs

VnDnnsLDR

)s(U

)s(V

−⋅−++⋅++⋅

⋅+⋅+⋅+=

−⋅−++⋅++⋅

⋅+⋅++−−=

1111

211

1111

1111

2222

2

22222

22

TAPPED-BOOST 2

( ) ( )( )( ) ( ) ( ) ( )

( ) ( )( )( ) ( ) ( ) ( )1111

111

1111

111

22

22

+⋅−++⋅++⋅

+−⋅+=

+⋅−++⋅++⋅

+−⋅⋅−=

'nDR'nsL'nCRLs

D'nCsR

)s(gV

)s(I

'nDR'nsL'nCRLs

D'nRD

)s(gV

)s(V

TTTTTT

TTT_

_

TTTTTT

TTT_

_

( )[ ] ( )( )( )( ) ( ) ( )

[ ] ( )( )( )( ) ( ) ( )111

112

111

111

22

222

2

+⋅−⋅−++

⋅+−⋅+=

+⋅−⋅−++

⋅+−⋅−−=

'nDDRsLCRLs

VD'nCsR

)s(U

)s(I

'nDDRsLCRLs

VD'nsLDR

)s(U

)s(V

TTTTTTT

gTTT

_

_

TTTTTTT

gTTT

_

_


Página 46 de 56

2.3 Análisis dinámico de la respuesta frecuencial. 2.3.1 Introducción. Los circuitos comentados anteriormente son circuitos de 2º orden, por tanto su función de transferencia es la siguiente:

22 2 nn wws

A)s(G

++=

ξ (2.73) El resultado obtenido si se aplica una entrada escalón es la siguiente:

Fig. 2.15 Respuesta temporal de un circuito de 2º orden.

Y sus variables son: TP Tiempo de pico TS Tiempo de establecimiento MPt Respuesta de pico

21

2

1

44

1

ξξ

ωξτ

ξω

π

−−+=

⋅==

−⋅=

/wPt

nS

n

P

neM

T

T


Página 47 de 56

A medida que ξ disminuye, las raices de las red se aproximan al eje imaginario y la respuesta se vuelve cada vez más oscilatoria. Tal y como se muestra en la siguiente gráfica, los polos deben estar en la parte izquierda del eje imaginario para que la respuesta sea estable La gráfica muestra como será la respuesta según la situación de sus polos en el diagrama polo-cero.

X

X

Fig. 2.16 Esquemas de un diagrama polo-cero y sus respuestas temporales en función de sus polos y ceros.

Imag

Real


Página 48 de 56

Pero en coeficiente de amortiguamiento (ξ) y la frecuencia natural (wn) son dependientes tal y como podrá observarse en la siguiente gráfica. Donde se ve la relación para un sistema de segundo orden:

Fig. 2.17 Dependencia entre coef. de amortiguamiento (ξ) y la frecuencia natural (wn)

Y para tener una mejor percepción de cómo influye el coeficiente de amortiguamiento ξ veremos la siguiente respuesta transitoria para una entrada escalón:

Fig. 2.18 Diferentes tipos de respuesta temporal dependiendo del valor de ξ.

A partir de las funciones de transferencia halladas anteriormente se va a realizar un estudio dinámico de dichos sistemas.


Página 49 de 56

2.3.2 Dinámica comparada: Topologías elevadoras. Para realizar un estudio del comportamiento dinámico de un circuito se debe comparar sus respectivas funciones de transferencia modeladas en pequeña señal. Se va a dar paso al análisis comparativo entre los modelos elementales y los analizados en dicho proyecto (denominados “Tapped”) dependiendo de la frecuencia de oscilación (wd) y de el coeficiente de amortiguamiento (2ξξ wn).

A

t

22 2 nn wws

A)s(G

++=

ξ

Fig. 2.19 Esquema circuito de 2º orden.

• BOOST IDEAL.- A partir de la función de transferencia básica, a continuaciòn se obtiene los siguientes resultados.

( )( )

( )

−=

=

−++

⋅−

==

BB

Bn

BBn

BB

B

BB

BB

B_

_

CL

Dw

CRw

CL

D

CR

ss

CL

D

)s(gV

)s(V)s(G

2

22

1

12

1

11

ξ

TAPPED BOOST1.-

( ) ( )( ) ( ) ( )

( )( )

( )( )

( )( )

+⋅

−=

+⋅

−=

=+⋅

+⋅=

−++⋅++⋅

+⋅⋅−=

2

2

2

2

2

2

2222

1

1

1

1

1

1

12

111

11

nCL

D

nCRL

DRw

CRnCRL

nLw

DRnsLnCRLs

nDRD)s(G

TT

T

TTT

TTn

TTTTT

Tn

TTTTTT

TTT

ξ

Vin Vout


Página 50 de 56

A partir de ahora con los valores obtenidos se deduce la similitud entre los modelos Tapped y los ideales. En la siguiente figura se observa que la única diferencia entre dichos circuitos es la bobina “L1”. Para ello se hace tender a cero para reducir en circuito Tapped a uno ideal. Así se obtiene una reducción al caso del convertirdor elemental.

002

11 === →=

L

L

N

NnL oIDEAL_CASO

Por tanto:

( )( )

( )( )

( )( )

( ) ( )

−=−=+⋅

−=+⋅

−=

==

+⋅+⋅=

→

4444 84444 76

44 844 76

ESEQUIVALENT

BB

B

TT

T

TT

T

TTT

TTn

ESEQUIVALENT

BBTTTTT

Tn

CL

D

CL

D

nCL

D

nCRL

DRw

CRCRnCRL

nLw

n

22

2

2

2

2

2

11

1

1

1

1

11

1

12

0

ξ

Por lo cual para un comportamiento dinámico equivalente entre dichos circuitos se debe cumplir lo siguiente:

BBTTTTBB

n CRCRCRCR

w =→==11

2ξ (2.74)

( )( )

( ) ( )( )

( )BB

B

TT

T

BB

B

TT

Tn CL

D

nCL

D

CL

D

nCL

Dw

2

2

22

2

2 1

1

11

1

1 −=

+⋅

−→

−=

+⋅

−=

(2.75)


Página 51 de 56

• BOOST IDEAL.- A partir de la función de transferencia básica, a continuaciòn se obtiene los siguientes resultados.

( )( )

( )

−=

=

−++

⋅−

==

BB

Bn

BBn

BB

B

BB

BB

B_

_

CL

Dw

CRw

CL

D

CR

ss

CL

D

)s(gV

)s(V)s(G

2

22

1

12

1

11

ξ

TAPPED BOOST2.-

( ) ( )( )( ) ( ) ( ) ( )

( )( )

( ) ( )( )

( )

−=+⋅

+⋅−=

=+⋅

+⋅=

+⋅−++⋅++⋅+−⋅⋅−=

TT

T

TTT

TTn

TTTTT

Tn

TTTTTT

TTT

CL

D

'nCRL

'nDRw

CR'nCRL

'nLw

'nDR'nsL'nCRLs

D'nRD)s(G

22

22

11

11

11

12

1111

111

ξ

A partir de ahora con los valores obtenidos se deduce la similitud entre los modelos Tapped y los ideales. En la siguiente figura se observa que la única diferencia entre dichos circuitos es la bobina “L1”. Para ello la hacemos tender a cero para reducir en circuito Tapped a uno ideal. Así compararemos dichos resultados.

0021

11 =

+== →=

LL

L

N

N'nL

T

oIDEAL_CASO


Página 52 de 56

( )( )

( ) ( )( )

( ) ( )

−=

−=

+⋅+⋅−

=

==+⋅

+⋅=

→

4444 84444 76

44 844 76

ESEQUIVALENT

BB

B

TT

T

TTT

TTn

ESEQUIVALENT

BBTTTTT

Tn

CL

D

CL

D

nCRL

nDRw

CRCRnCRL

nLw

n

222 111

11

111

12

0

ξ

Como detalle de los resultado obtenidos se observa que ninguno de los dos parametros dinámicos (coef. de amortiguamiento y frecuenica de oscilación ) no dependen en ningún momento de la relación de transformación “n”.

BBTTTTBB

n CRCRCRCR

w =→==11

2ξ (2.76)

( ) ( ) ( ) ( )BB

B

TT

T

BB

B

TT

Tn

CL

D

CL

D

CL

D

CL

Dw

2222 1111 −=

−→

−=

−=

(2.77)


Página 53 de 56

2.3.3 Dinámica comparada: Topologías Reductoras. • BUCK IDEAL.- A partir de la función de transferencia básica, a continuaciòn se obtiene los siguientes resultados.

=

=

++

⋅==

BBn

BBn

BBBB

BB_

_

CLw

CRw

CLCR

ss

CL)s(gV

)s(V)s(G

1

12

111

2

ξ

TAPPED BUCK1.-

( ) ( )( ) ( ) ( ) ( )[ ]

( )( )

( ) ( )[ ]( )

( ) ( )[ ]( )

+⋅−++=

+⋅−++=

=+⋅

+⋅=

−++⋅++⋅++⋅+⋅+⋅⋅

=

2

2

2

2

2

2

2222

1

11

1

11

1

1

12

1111

11

nCL

DnD

nCRL

DnDRw

CRnCRL

nLw

DnDRnsLnCRLs

nnDDR)s(G

TT

TT

TTT

TTTn

TTTTT

Tn

TTTTTTT

TTT

ξ

Siguiendo los anteriores paso se realiza una reducción al caso ideal, tal como indica la siguiente figura:

002

11 === →=

L

L

N

NnL oIDEAL_CASO


Página 54 de 56

( )( )

( ) ( )[ ]( )

( ) ( )[ ]( )

==+⋅−++=

+⋅−++=

==+⋅

+⋅=

→

444 8444 76

44 844 76

CCTTTT

TT

TTT

TTTn

BBTTTTT

Tn

CLCLnCL

DnD

nCRL

DnDRw

CRCRnCRL

nLw

n

111

111

11

11

1

12

0

2

2

2

2

2

2ξ


BBTTTTBB

n CRCRCRCR

w =→== 112ξ

(2.78)

( ) ( )[ ]( )

( ) ( )[ ]( ) BBTT

TT

BBTT

TTn CLnCL

DnD

CLnCL

DnDw

1

1

111

1

112

2

2

2

=+⋅

−++→=

+⋅

−++=

(2.79)


Página 55 de 56

• BUCK IDEAL.- A partir de la función de transferencia básica, a continuaciòn se obtiene los siguientes resultados.

=

=

++

⋅==

BBn

BBn

BBBB

BB_

_

CLw

CRw

CLCR

ss

CL)s(gV

)s(V)s(G

1

12

111

2

ξ

TAPPED BUCK2.-

( )( ) ( ) ( )[ ]

( )( )

( )[ ]( )

( )[ ]( )

+⋅⋅−+

=+⋅⋅

−+=

=+⋅⋅

+⋅⋅=

−+⋅++⋅⋅++⋅⋅−+⋅⋅⋅

=

2

2

2

2

22

22

222222

1

1

1

1

1

1

12

111

1

nnCL

Dn

nnCRL

DnRw

CRnnCRL

nnLw

DnRnnsLnnCRLs

DnDRn)s(G

TT

T

TTT

TTn

TTTTT

Tn

TTTTTT

TTT

ξ

Siguiendo los anteriores paso se realiza una reducción al caso ideal, tal como indica la siguiente figura.:

∞=== →=2

12 0

L

L

N

NnL oIDEAL_CASO


Página 56 de 56

( )( )

( )[ ]( )

( )[ ]( )

( )

( )→

+

−+

→

=

+

−+

→

+⋅⋅−+=

+⋅⋅−+=

==+⋅⋅

+⋅⋅=

∞→

=

211

21

12

11

21

22

2

22

2

22

22

1

1

1

1

1

1

1

1

1

11

1

12

1

TTTT

TTL

Ln

T

TT

TT

TT

T

TT

Tn

BBTTTTT

Tn

L

L

L

LCL

DL

L

LC

L

LLC

DL

L

nnCL

Dn

nnCL

Dnw

CRCRnnCRL

nnLw

n

T

ξ


BBTTTTBB

n CRCRCRCR

w =→==11

2ξ (2.80)

( )

BBT

TT

TT

n LCLC

L

LLC

DL

L

w11

1

1

12

11

21

==

+

−+

= (2.81)


Página 1 de 25

3 Memoria de cálculo. 3.1 Topologías básicas: Rizados ∆∆ IL , ∆∆VC. El valor de las bobinas y condensadores han sido elegidos inicialmente. Por ello a continuación se realiza la obtención de los valores de los rizados en los componentes anteriormente comentados. Dichos incrementos les diferencian según el modo de trabajo del convertidor (Ton, Toff). BOOST.-

sTkHzf

RFCHL

µ

µµ

5020

4083666

==

Ω===

( )

( )A

DR

VgI

DD

XssM

VVout

VVin

L 2

21

140

20

1

21

21

12

40

20

22=

−⋅

=−

=

=→=−

=⇒=

=

=

(3.1)

A.tL

VcVgI

A.L

tVgI

Loff

Lon

75021050

10666

4020

75010666

2

105020

6

62

6

6

1

=⋅

⋅⋅

−=⋅

−=∆

≅⋅

⋅⋅

=⋅

=∆

−

−

−

−

Fig. 3.1 Simulación Pspice de la corriente en la

bobina en el Boost ideal.

V.V.tCR

Vc

C

IVcoff

V.V.tCR

VcVcon

L 303010

30301021050

401083

40

2

6

61

≈≅⋅

−=∆

≈−≅⋅

⋅⋅⋅

−=⋅−=∆−

−

Fig. 3.2 Simulación Pspice de la tensión en el condensador en el Boost ideal.


Página 2 de 25

BUCK.-

sTkHzf

RFCHL

µ

µµ

5020

1083666

==

Ω===

AR

VgDI

DXssM

VVout

VVin

L 210

4021

21

21

20

40

=⋅

=⋅

=

==⇒=

=

=

(3.2)

A.tL

VcI

A.tL

VcVgI

Loff

Lon

75021050

10666

20

75021050

10666

2040

6

62

6

61

=⋅

⋅⋅

−=⋅

−=∆

≅⋅

⋅⋅−

=⋅−

=∆

−

−

−

−


bobina en el Buck ideal.

( ) VtCR

Vc

nC

IVcoff

VtCR

Vc

C

IVcon

L

L

01

0

2

1

≅⋅

−

+⋅=∆

≅⋅

−=∆

Fig. 3.4 Simulación Pspice de la tensión en el

condensador en el Buck ideal.


Página 3 de 25

BUCK-BOOST (Reductor) .-

sTkHzf

RFCHL

µ

µµ

5020

1083666

==

Ω===

( )A

RD

VgDI

DDDDD

DXssM

VVout

VVin

L 31

31

132121

121

20

40

2=

⋅−

⋅=

=→=→=−→=−

=⇒=

=

=

(3.3)

AtL

VcI

AtL

VgI

Loff

Lon

13

10502

10666

20

131050

10666

40

6

62

6

61

=⋅⋅⋅⋅

=⋅=∆

≅⋅⋅⋅

=⋅=∆

−

−

−

−


bobina en el Buck-Boost (Reductor).

V.V.tCR

Vc

C

IVcoff

V.V.tCR

VcVcon

L 404010

404010

2

1

≈≅⋅

−=∆

≈−≅⋅

−=∆


condensador en el Buck-Boost (Reductor).


Página 4 de 25

BUCK-BOOST (Elevador) .-

sTkHzf

RFCHL

µ

µµ

5020

4083666

==

Ω===

( )).(A

RD

VgDI

DDDDD

DXssM

VVout

VVin

L 4331

3

223222

12

40

20

2 =⋅−

⋅=

=→=→=−→=−

=⇒=

=

=

AtL

VcI

AtL

VgI

Loff

Lon

131050

10666

40

13

10502

10666

20

6

62

6

61

=⋅⋅⋅

=⋅=∆

≅⋅⋅⋅⋅

=⋅=∆

−

−

−

−


bobina en el Buck-Boost (Elevador).

V.V.tCR

Vc

C

IVcoff

V.V.tCRVc

Vcon

L 404010

404010

2

1

≈≅⋅

−=∆

≈−≅⋅

−=∆


condensador en el Buck-Boost (Elevador).


Página 5 de 25

TABLAS COMPARATIVAS DE CONVERTIDORES ELEMENTALES Para una mejor comparación de valores se ha encontrado oportuno la creación de una tabla resumen que a continuación es mostrada.

BOOST BUCK B-B (Red.) B-B (Elev.)

Vi (V)

20 40 40 20

Vo (V) 40 20 20 40

D ½ 1/2 1/3 2/3

IL (A) 2 2 3 3

∆∆ ILon (A)

0.75 0.75 1 1

∆∆ ILoff (A)

0.75 0.75 1 1

∆∆ VCon (V)

0.3 0 0.4 0.4

∆∆ VCoff (V)

0.3 0 0.4 0.4

Fig. 3.9 Tabla resumen de los valores de los rizados de los convertidores elementales.


Página 6 de 25

Topologías “ Tapped ”: Rizados ∆∆ IL , ∆∆VC.

El valor de las bobinas y condensadores son elegidos inicialmente, por tanto ahora se observarán las características que aportan los diferentes circuitos, según su tipo de conexionado. Y finalmente se obtendrán tablas comparativas de resultados. TAPPED-BOOST1.-

sTkHzf

RFCHLHL

µ

µµµ

5020

4083333333 21

==

Ω====

( )

( )( )( )

ADR

VgnDnI

DDDDD

DnXssM

VVout

VVin

L 3

31

140

2034

2

1

11

31

1322121

12

40

20

22=

−⋅

⋅⋅=

−

++=

=→=→−=+→=−

+=⇒=

=

=

(3.5)

( ) A.tLn

VcVgI

HLL:Entonces

AL

tVgI

TLoff

T

Lon

503

10502

106662

40201

6662

110333

31050

20

6

62

1

6

6

1

1

=⋅⋅⋅⋅⋅

−=⋅⋅+

−=∆

=⋅=

≅⋅

⋅⋅=

⋅=∆

−

−

−

−

µ

Fig. 3.10 Simulación Pspice de la corriente en la bobina en el Tapped-Boost 1.

( ) ( ) ADn

IDII L

Li 232

23

31

311

=⋅+⋅=−⋅+

+⋅=

( ) V.tCR

Vc

nC

IVcoff

V.tCR

VcVcon

L 201

2031050

401083

40

2

6

61

≅⋅

−

+⋅=∆

≅⋅

⋅⋅⋅

−=⋅−=∆−

−


condensador en el Tapped-Boost 1.


Página 7 de 25

TAPPED-BOOST2.-

sTkHzf

RFCHLHL

µ

µµµ

5020

4083333333 21

==

Ω====

( )( )( )

( )( )

( )( ) ( )

AVgnDR

nDI

DD

D

nD

DnXssM

VVout

VVin

L 3

231

40

131

11

11

32

2111

21111

240

20

22 =

⋅

⋅

+=⋅

+−+⋅−

=

=→⋅−+−

→=+−+−

=⇒=

=

=

(3.6)

( )

A.

tL

VcVgI

A.tnL

VgI

Loff

TLon

131050

1033333

4020

503

10502

210666

201

6

621

6

61

=⋅

⋅⋅

−=⋅

−=∆

≅⋅⋅

⋅⋅⋅

=⋅+⋅

=∆

−

−

−

−

Fig. 3.12 Simulación Pspice de la corriente en la bobina en el Tapped-Boost 2.

( ) ( ) ADIDn

II L

Li 21

1=−⋅+⋅

+=

V.tCR

Vc

C

IVcoff

V.tCR

VcVcon

L 40

403

10502

401083

40

2

6

61

≅⋅

−=∆

≅⋅⋅

⋅⋅⋅

−=⋅−=∆−

−


condensador en el Tapped-Boost 2.


Página 8 de 25

TAPPED-BUCK1.-

sTkHzf

RFCHLHL

µ

µµµ

5020

1083333333 21

==

Ω====

( )

( )( )

).(ARDn

VgDnI

DDDDDn

DnXssM

VVout

VVin

L 733

10131

4031

4

1

1

31

134121

11

21

20

40

22

2

=

⋅

+

⋅⋅=

⋅+⋅⋅+=

=→=→=+→=+⋅+=⇒=

=

=

( ) A.tLn

VcI

AtL

VcVgI

TLoff

Lon

50310502

106662

201

131050

10333

2040

6

62

6

612

=⋅⋅⋅⋅⋅

−=⋅⋅+

−=∆

≅⋅⋅⋅−=⋅−=∆

−

−

−

−

Fig. 3.14 Simulación Pspice de la corriente en la bobina en el Tapped-Buck 1.

( )( )

AR

Vg

Dn

DnIi 1

10131

4031

4

1

12

2

2

22=

⋅

+

⋅

⋅

=⋅+

⋅+=

( ) V.tCR

Vc

nC

IVcoff

V.tCR

Vc

C

IVcon

L

L

201

20

2

1

≅⋅

−

+⋅=∆

≅⋅

−=∆


condensador en el Tapped-Buck 1.


Página 9 de 25

TAPPED-BUCK2.-

sTkHzf

RFCHLHL

µ

µµµ

5020

1083333333 21

==

Ω====

( )( )

ARDn

VgDnnI

DDDDDn

VgDnXssM

VVout

VVin

L 31

1

32

232221

121

20

40

2

2

=⋅−+⋅⋅⋅+=

=→=→=−→=−+⋅

=⇒=

=

=

(3.8)

( )

AtLn

VcI

A.tLn

VcVgI

Loff

TLon

131050

10333

20

503

10502

106662

20401

6

622

6

61

=⋅⋅⋅

−=⋅⋅

−=∆

≅⋅⋅⋅⋅⋅

−=⋅+−=∆

−

−

−

−

Fig. 3.16 Simulación Pspice de la corriente

en la bobina en el Tapped-Buck 2.

( )A

R

Vg

Dn

nDIi 1

1032

2

4032

1 2

2

2

22=

⋅

−

⋅

=⋅−+⋅=

( )

V.tCR

Vc

nC

IVcoff

V.tCR

Vc

Cn

IVcon

L

L

20

201

2

1

≅⋅

−=∆

≅⋅

−

⋅+=∆

Fig. 3.17 Simulación Pspice de la tensión

en el condensador en el Tapped-Buckt 2.


Página 10 de 25

TABLAS COMPARATIVAS DE CONVERTIDORES TAPPED Se realiza una recopilacíon de todos los datos obtenidos anteriormente. TAPPED-BOOST1 TAPPED-BOOST2 TAPPED-BUCK1 TAPPED-BUCK2

Vi (V) 20 20 40 40

Vo (V) 40 40 20 20

D

1/3 2/3 1/3 2/3

Ii (A)

2 2 1 1

IL (A) 3 3 3 3

∆∆ ILon (A)

1 0.5 1 0.5

∆∆ ILoff (A)

0.5 1 0.5 1

∆∆ VCon (V)

0.2 0.4 0.2 0.2

∆∆ VCoff (V)

0.2 0.4 0.2 0.2

Fig 3.18 Tabla comparativa de los valores de los rizados en la topologías “Tapped”.


Página 11 de 25

3.3 Respuesta frecuencial y temporal con “ Matlab ”.

Respuesta temporal, diagrama de Bode y Polo-Cero.

A

t

22 2 nn wws

A)s(G

++=

ξ

Fig. 3.19 Representación de la respuesta temporal de una función de transferencia de 2º orden.

Mediate el programa informático de simulación de circuitos denominado “Matlab” se obtienen la respuesta temporal y los diagramas de Bode y de Polo-Cero de los diferentes prototipos. Con ello vemos la estabilidad de los circuitos y sus comportamientos frecuenciales y temporales. Para obtener los resultados los circuitos alternativos son excitados con una respuesta impulsional, como la mostrada en la Fig. 3.19. La tensión de salida Vout presenta un amortiguamiento en la que el valor tiende al esperado. Se observará que los diagramas de Bode que la frecuencia en la que se trabaja es apta para el análisis de las funciones de transferencia. O sea, que tiene un comportamiento linealizado. Y el diagrama Polo-Cero presenta estabilidad ya que los polos aparecen en el semiplano izquierdo. Por tanto nuestros circuitos convergen a los valores deseados y por ello son estables.

Vin Vout


Página 12 de 25

3.3.1 Topologías elevadoras: Boost y modelos Tapped - Boost. BOOST IDEAL:

( )( )

−++

⋅−

==

BB

B

BB

BB

B_

_

CL

D

CR

ss

CL

D

)s(gV

)s(V)s(G

22 1

11 (3.9)

DB = 1 / 2 CB = 83 µµF LB = 333 µµH RB= 40 ΩΩ

Respuesta temporal.

Fig. 3.20 Repuesta temporal.


Página 13 de 25

Diagrama Polo-Cero.

Fig 3.21 Diagrama polo-cero.

Diagrama de Bode.

Fig. 3.22 Diagrama de Bode.


Página 14 de 25

TAPPED-BOOST 1 :

( )( )

−++

⋅−

==

BB

B

BB

BB

B_

_

CL

D

CR

ss

CL

D

)s(gV

)s(V)s(G

22 1

11 (3.10)

DT = 1 / 3 CT = 83 µµF LT = 333 µµH RT= 40 ΩΩ

Respuesta temporal.

Fig 3.23 Respuesta temporal.


Página 15 de 25

Diagrama Polo-Cero.

Fig. 3.24 Diagrama polo-cero.

Diagrama de Bode.



Página 16 de 25

TAPPED-BOOST 2:

( )( )

−++

⋅−

==

BB

B

BB

BB

B_

_

CL

D

CR

ss

CL

D

)s(gV

)s(V)s(G

22 1

11 (3.11)


Respuesta temporal.

Fig. 3.26 Respuesta temporal.


Página 17 de 25

Diagrama Polo-Cero.


Diagrama de Bode.

Fig.3.28 Diagrama de Bode.


Página 18 de 25

3.3.2 Topologías Reductoras: Buck y Tapped – Buck. BUCK IDEAL:

++

⋅==

BBBB

BB_

_

CLCR

ss

CL)s(gV

)s(V)s(G

1

11

2 (3.12)

DB = 1 / 2 CB = 83 µµF LB = 333 µµH RB= 10 ΩΩ

Respuesta temporal.



Página 19 de 25

Diagrama Polo-Cero.

Fig 3.30 Diagrama polo-cero.

Diagrama de Bode.

Fig . 3.31 Diagrama de Bode.


Página 20 de 25

TAPPED-BUCK 1:

( ) ( )( ) ( ) ( ) ( )[ ]2222 1111

11

TTTTTTT

TTT

DnDRnsLnCRLs

nnDDR)s(G

−++⋅++⋅++⋅+⋅+⋅⋅=

(3.13)


Respuesta temporal



Página 21 de 25

Diagrama Polo-Cero.


Diagrama de Bode.



Página 22 de 25

TAPPED-BUCK 2:

( )( ) ( ) ( )[ ]222222 111

1

TTTTTT

TTT

DnRnnsLnnCRLs

DnDRn)s(G

−+⋅++⋅⋅++⋅⋅

−+⋅⋅⋅=

(3.14)


Respuesta temporal.

Fig 3.35. Respuesta temporal.


Página 23 de 25

Diagrama Polo-Cero.


Diagrama de Bode.



Página 24 de 25

3.3.3 Parámetros dinámicos y tabla resumen. Con los mismos valores de componentes que anteriormente han sido hallados se realiza una simulación mediante el programa “Matlab”. Son realizados unos programas en la cual se obtienenlos distintos resultados. TP Tiempo de pico TS Tiempo de establecimiento MPt Respuesta de pico

21

2

1

4

1

ξξ

ωξ

ξω

π

−−+=

⋅=

−⋅=

/wPt

nS

n

P

neM

T

T

(3.15)

TOPOLOGÍAS

ξξ wn (103 rad/s) TP(ms) MPt TS(ms)

BOOST

0.0709

2.13 1.478 1.799 26.487

TAPPED-BOOST1

0.0752

2 1.575 1.789 26.595

TAPPED-BOOST2

0.0752

2 1.575 1.789 26.595

BUCK

0.142

4.25 0.746 1.637 6.628

TAPPED-BUCK1

0.15

4.01 0.792 1.476 6.650

TAPPED-BUCK2

0.15

4.01 0.792 1.476 6.650

Fig. 3.38 Tabla resumen de los parámetros dinánicos del sistema. Como puede observarse tanto los Tapped elevadores como los Tapped reductores respectivamente, tienen el mismo valor de sus coeficientes de amortiguamiento y de sus frecuencias naturales. Eso indica que dinàmicamente son equivalentes. O sea, que su sobrepico es aproximadamente el mismo y su tiempo de establecimiento también. La diferencia entre ellos es el “Duty-cycle” respectivametne de los elevadores y lo mismo en los reductores. La diferencia dinámica de elevadores y reductores se debe en su mayoría a la carga. Ya que como puede observarse que si la carga “R” aumenta la frecuencia natural disminuye, igual que su coeficiente de amortiguamiento. Puede observarse que los circuitos reductores son más rápidos, su respuesta de pico es menor y se estabiliza mucha antes que los circuitos elevadores.

de 25

TOPOLOGÍAS

Función de Transferencia

Coef. amort.

ξξ

Fec. natur. wn (103 rad/s)

T. pico TP (ms)

Sobrep. MPt

T.Est. TS (ms)

BOOST

( )( )

−++

⋅−

==

BB

B

BB

BB

B_

_

CL

D

CR

ss

CL

D

)s(gV

)s(V)s(G

22 1

11 0.0709 2.13 1.478 1.799 26.487

TAPPED-BOOST1

( ) ( )( ) ( ) ( )2222 111

11

TTTTTT

TTT_

_

SDRnsLnCRLs

nDRD

)s(gV

)s(VG

−++⋅++⋅

+⋅⋅−== 0.0752 2 1.575 1.789 26.595

TAPPED-BOOST2

( ) ( )( )( ) ( ) ( ) ( )1111

11122 +⋅−++⋅++⋅

+−⋅⋅−=='nDR'nsL'nCRLs

D'nRD

)s(gV

)s(VG

TTTTTT

TTT_

_

S

0.0752 2 1.575 1.789 26.595

BUCK

++

⋅==

BBBB

BB_

_

CLCR

ss

CL)s(gV

)s(V)s(G

1

11

2 0.142 4.25 0.746 1.637

6.628

TAPPED-BUCK1

( ) ( )( ) ( ) ( ) ( )[ ]2222 1111

11

TTTTTTT

TTT

DnDRnsLnCRLs

nnDDR)s(G

−++⋅++⋅++⋅

+⋅+⋅⋅=

0.15 4.01 0.792 1.476 6.650

TAPPED-BUCK2

( )( ) ( ) ( )[ ]222222 111

1

TTTTTT

TTT

DnRnnsLnnCRLs

DnDRn)s(G

−+⋅++⋅⋅++⋅⋅−+⋅⋅⋅=

0.15 4.01 0.792 1.476 6.650


Página 1 de 30

4 -Simulación y resultados experimentales. A continuación se observan los resultados obtenidos mediante el programa de simulación de circuitos Pspice, de las diferentes topologías. 4.1 Topologías básicas (Pspice).

Buck.-

Boost.-


Página 2 de 30

4.2 Topologías “ Tapped “. Se comparan los valores obtenidos simulados con el inductor Tapped y en su lugar un transformados ideal .

BOBINA ACOPLADA TRAFO IDEAL ACOPLADO Tapped Buck 1


Página 3 de 30

BOBINA ACOPLADA TRAFO IDEAL ACOPLADO

Tapped Buck 2


Página 4 de 30


Tapped Boost 1


Página 5 de 30


Tapped Boost 2


Página 7 de 30

4.3 Prototipos experimentales. Tras el proceso de insolación de las placas y tras soldar los diferentes componentes se obtienen los prototipos reales que a continuación son mostrados.

Tapped Boost. Tapped Buck

Fig. 4.1 Prototipos experimentales “Tapped”. Los componentes de un convertidor son los siguientes:

Figura 4.2 Esquema básico de un convertidor.

• Fuente • Almacenador de energía • Modulador de anchura de pulsos • Filtro de salida • Carga


Página 8 de 30

FUENTE CONVERTIDOR

BUCK ALMACENADOR

ENERGÍA

CARGA

Fig. 4.3 Prototipo Tapped Buck (Reductor).


Página 9 de 30

FUENTE CONVERTIDOR

BOOST ALMACENADOR

ENERGÍA

CARGA

Fig. 4.4 Prototipo Tapped-Boost (Elevador).


Página 10 de 30

4.4 Comparación Simulación – Prototipos. Seguidamente mediante unas gráficas se realizará una comparativa entre valores obtenidos en simulaciones con el programa de simulación de esquemas circuitales Pspice y las gráficas obtendidas mediante el osciloscopio en el laboratorio. Con ello se pretende observar las similitudes y diferencias en ambos casos. 4.4.1 Buck elemental.

GRAFICAS REALES GRAFICAS SIMULACIÓN

Corriente en la bobina del convertidor. Simulación Pspice de la corriente en la bobina en el Buck ideal.

Tensión Vc del condensador. Simulación Pspice de la tensión Vc del condensador.

Fig 4.5 Comparativa gráficas reales con simuladas.


Página 11 de 30

En la siguiente tabla resumen se incluyen los valores importantes obtenidos a partir de los resultados de las gráficas anteriormente vistas. Con ello se pretende realizar un

análisis cuantitativo de los resultados.

Rendimiento 9270.

Pout

Pin==η

BUCK REAL BUCK SIMULADO

Vi (V) 39.8 40

Vo (V)

20 20

D

½ ½

IL (A) 1.71 2

∆∆ ILon (A)

0.54 0.75

∆∆ ILoff (A)

0.54 0.75

∆∆ VCon (V)

0.1 0.05

∆∆ VCoff (V)

0.1 0.05

Fig. 4.6 Tabla resumen de los valores obtenidos.


Página 12 de 30



Corriente del primario (IL1) de la bobina acoplada.

Corriente del secundario (IL2) de la bobina acoplada.

Tensión en el condensador Vc.



Página 13 de 30

Rendimiento 930.

Pout

Pin==η

TAPPED BUCK 1 REAL TAPPED BUCK 1 SIMULADO

Vi (V) 39.9 40

Vo (V) 19.9 20

n 1 1

D

33.39 % 1/3

Ii (A)

1.71 1

∆∆ ILon (A)

1 1

∆∆ ILoff (A)

0.5 0.5

∆∆ VCon (V)

0.36 0.2

∆∆ VCoff (V)

0.36 0.2



Página 14 de 30

Tapped Buck 2.



Corriente del secuandario (IL2) de la bobina acoplada.

Tensión en el condensador del Tapped Buck 2.



Página 15 de 30

Rendimiento 8980.

Pout

Pin==η

TAPPED BUCK 2 REAL TAPPED BUCK 2 SIMULADO

Vi (V) 39.7 40

Vo (V) 19.8 20

n 1 1

D

66.72 % 2/3

Ii (A)

1.03 1

∆∆ ILon (A)

0.6 0.5

∆∆ ILoff (A)

1 1

∆∆ VCon (V)

0.215 0.2

∆∆ VCoff (V)

0.215 0.2



Página 16 de 30

Boost ideal .


Corriente en la bobina del Boost ideal.

Tensión Vc del condensador.



Página 17 de 30

Rendimiento 8500.

Pout

Pin==η

BOOST REAL BOOST SIMULADO

Vi (V) 19.9 20

Vo (V)

39.3 40

D

½ ½

IL (A) 1.65 2

∆∆ ILon (A)

0.94 0.75

∆∆ ILoff (A)

0.94 0.75

∆∆ VCon (V)

0.35 0.3

∆∆ VCoff (V)

0.35 0.3



Página 18 de 30

4.4.5 Tapped-Boost 1.




Tensión en el condensador del Tapped Boost 1.



Página 19 de 30

Rendimiento 940.

Pout

Pin==η

TAPPED BOOST 1 REAL TAPPED BOOST 1 SIMULADO

Vi (V) 20.1 20

Vo (V)

38.8 40

n 1 1

D 33.61 % 1/3

Ii (A) 1.69 2

∆∆ ILon (A)

2 1

∆∆ ILoff (A)

1 0.5

∆∆ VCon (V)

0.21 0.2

∆∆ VCoff (V)

0.21 0.2



Página 20 de 30

Tapped Boost 2.




Tensión en el condensador del Tapped Boost 2.



Página 21 de 30

Rendimiento 8260.Pout

Pin==η

TAPPED BOOST 2 REAL TAPPED BOOST 2 SIMULADO

Vi (V)

20.1 20

Vo (V)

38.9 40

n 1 1

D 66.67 % 2/3

Ii (A) 1.86 2

∆∆ ILon (A)

0.9 0.5

∆∆ ILoff (A)

2 1

∆∆ VCon (V)

0.36 0.4

∆∆ VCoff (V)

0.36 0.4


Los valores de la tensión de entrada y salida son hallados mediante el osciloscopio del laboratorio. El valor de la tensión de entrada no es exacto al simulado debido a las propias variaciones de la fuente de alimentación. Mediante la manipulación del único componente a manipular, un potenciometro conseguimos variar el duty-cycle hasta obtener el valor exácto a utilizar. Los siguientes resultados presentan diferencias debido a que los componentes dejan de ser ideales y aparecen una serie de perdidas (por elementos que no siguen un comportamiento lineal, pérdidas por efecto joule, pérdidas en las mismas pistas del circuito impreso,...). Una mayor diferencia presenta la tensión en el condensador Vc en las gráficas reales. No se comporta como idealmente es la carga y descarga de un condensador. Ello se debe a que en la simulación, la carga que utilizamos es ideal. En cambio, realmente en la carga, tanto la resistencia posee valores parásitos y el condensador, que es el más afectado posee parásitos inductivos, capacitivos y resistivos. Por ello se obtiene un acoplo de valores parásitos distorsionando la señal. Aunque para los valores incrementales obtenidos ∆Vc, presentan cierta similitud con los simulados con el programa Pspice.


Página 22 de 30

Comportamiento frecuencial (ancho de banda) de diferentes tipos de condensadores. A

w Condensador electrolítico. Condensador ideal. Condensador de poliester (varios en paralelo).

Fig. 4.17 Diagrama de Bode para diferentes tipos de condensadores. Dependiendo del tipo de condensador se poseen diferentes comportamiento en elevadas frecuencias de trabajo. El condensador utilizado en los diferentes prototipos poseen buenas condiciones de trabajo.

Fig. 4.18 Modelo real de un condensador en paralelo con la carga.

Se observa por tanto que el comportamiento real no es solo la de un condensador, sino que se le unen una serie de valores parásitos como la tensión que cae en Lc y Rc.


Página 23 de 30

4.4.7 Otras gráficas. Se han obtenido mediante el estudio en el laboratorio gracias a la ayuda de un osciloscopio las siguientes gráficas. Con ello se pretende una mejor comprensión de los prototipos debido a que se realiza un análisis modular. Tapped Boost 1: Tensión salida CA3130:

Tensión Vgs:


Página 24 de 30

Tensión salida Vout:

Tensión salida ICL8038:


Página 25 de 30

Tapped Boost 2: Tension salida CA 3130:

Tensión Vgs:


Página 26 de 30

Tension de Salida Vout:



Página 27 de 30

Tapped-Buck 1: Tensión de salida del CA 3130:

Tensión Vgs del MOSFET:


Página 28 de 30

Tensión de salida del convertidor:



Página 29 de 30

Tapped-Buck 2: Tensión de salida de CA 3130:

Tensión Vgs del MOSFET :


Página 30 de 30

Tensión de salida del convertidor:


P.F.C: Convertidores DC/DC: Análisis de prototipos “Tapped” en lazo abierto Memoria Descriptiva

Página 1 de 1

5 Conclusiones. Existen pocas aplicaciones que justifiquen el diseño y la creación de nuevos

convertidores ó topologías conmutadas. Para la mayor parte de las aplicaciones ya existen topologías adecuadas suficientemente simples, incluso en la mayoría de las veces convertidores como el Buck, Boost y Buck-Boost pueden ser utilizados ventajosamente en aplicaciones concretas. Circuitos más complicados como el Forward, el Flyback o el Cuk no serían necesarios. Es cierto que el Cuk ò convertidor de topología óptima presente ventajas como ausencia de corrientes pulsantes en la entrada y en la salida, pero presenta desventajas como una dinámica más compleja y mayores pérdidas. El forward (Buck) y el flyback (Buck-Boost) tienen como ventajas permitir múltiples salidas aisladas entre sí y de la entrada, pero su principal inconveniente es el complejo diseño de los transformadores. Uno de las maneras más simples de alterar, en aquellas aplicaciones en que sea preciso, las características de los convertidores elementales es el “Tappeado” del inductor presente en dichos convertidores. Entre los beneficios que pueden ser obtenidos destacan mejores propiedades de regulación cruzada, niveles mas bajos de EMI, reducción en el stress de algunos componentes, y en algunos casos la eliminación ó desplazamiento de polos del semiplano izquierdo y de ceros del semiplano derecho en las funciones de pequeña señal. De esta forma, las topologías “Tapped” pueden tener un lazo de control más estable, ó de diseño más fácil.

En este presente proyecto se ha realizado un análisis en lazo abierto de las

topologías convertidoras Tapped. Dichas topologías se han comparado con las células de conversión elementales de las cuales derivan, los convertidores Buck, Boost, y Buck-Boost. Dicho análisis incluye el modelo en pequeña señal de las cuatro topologías Tapped utilizadas, modelo dinámico que también se ha comparado con el de los correspondientes convertidores elementales. De esta forma se ha podido observar como influye el uso de inductores con tomas intermedias en la dinámica de los convertidores Tapped llegando a establecer relaciones entre los valores de los componentes de ambos tipos de topologías para que presenten dinámicas equivalentes. Este análisis tanto estático como dinámico, ha sido validado mediante simulaciones Pspice y Matlab, mientras que herramientas como Wmaple han servido de ayuda para el cálculo de algunas funciones de transferencia de dichos modelos dinámicos. Otro aspecto interesante ha sido la realización de dos prototipos experimentales de 100 W. Uno de los prototipos permite validar experimentalmente los análisis comparativos entre las topologías Buck y Tapped-Buck mientras que el segundo verifica las topologías Boost y Tapped-Boost. Hemos constatado a partir de los resultados experimentales, que concuerdan con las simulaciones realizadas, la corrección y validez en los análisis realizados. Nos hemos esforzado en presentar las gráficas de osciloscopio al lado de los correspondientes de simulación para resaltar precisamente esa concordancia.


Página 1 de 8

6. Planos y Presupuesto. 6.1 Esquemáticos Drivers. A continuación se observan los diferentes esquemas circuitales de los drivers de control de los convertidores nombrados en el presente proyecto. Su función es la de regular el intercambio de energía entre fuente y carga. A ello se le denomina Duty cicle. Circuitalmente lo logramos creando una señal triangular (denominada “diente de sierra”) y mediante un comparador trabajando en saturación, manipulado por una señal constante provenida de un potenciometro. Prototipos Buck (Reductores) :

Fig. 6.1 Prototipo Buck.

Prototipos Boost (Elevadores) :

Fig. 6.2 Prototipo Boost.


Página 2 de 8

Diseño Placas. Para el diseño de las placas se ha utilizado el programa “Protel Design System”, con el cual se han creado librerías para los diferentes componentes y eligiendo un grosor considerable de las pistas se obtienen los diferentes diseños: Diseño Tapped Buck. A continuación se observan los esquemáticos de las placas realizadas con el programa “Protel Design System”.

Fig. 6.3 Diseño de placa del modelo Tapped Buck con componentes y sin ellos.

Fig. 6.4 Esquemas de la carga y del transformador de dicho convertidor.


Página 3 de 8

El resultado final obtenido es el mostrado a continuación. La placa ya está lista para ser insolada y obtener así la elaboración de la placa.

Fig. 6.5 Esquema real de la placa a insolar del Tapped Buck.


Página 4 de 8

Diseño Tapped Boost. Igualmente que el anterior caso se siguen los mismos pasos para la elaboración de la siguiente placa:

Fig. 6.6 Diseño de placa del modelo Tapped Buck con componentes y sin ellos.

Fig. 6.7 Esquemas de la carga y del transformador de dicho convertidor.


Página 5 de 8

Fig. 6.8 Esquema real de la placa a insolar del Tapped Boost.


Página 6 de 8

6.2 Posibles drivers alternativos. Una posible solución a adoptar es la que a continuación es mostrada. Una posibilidad podría haber sido la de escoger un driver más reducido. Con el circuito integrado IR2115 el esquema circuital del driver en este caso de los prototipos Buck (Reductores) se hubieran visto reducidos. Esta idea fue descartada ya que se pretendía obtener un driver realizado con componentes pasivos y no integrado. Las características de dicho integrado son las mostradas a continuación:

IR2115

Puede observarse que su conexión es muy fácil de realizar.


Página 7 de 8

6.3 Presupuesto. A continuación se realiza un cálculo aproximado del coste circuital de dicho proyecto. Para ello a partir de los valores de los diferentes componentes utilizados se realiza la siguiente tabla de precios.

TOPOLOGÍA ELEVADORA

Componente

Cantidad Precio

unitario Total (Euros)

BC 337-338 3 0.10 0.30

Condens. electrolítico 4 0.06 0.24

Resistencia 3 0.06 0.18

Diodos Zener 1 0.06 0.06

ICL 8038 1 4.70 4.70

CA 3130 1 1.35 1.35

Condensador Poliester 4 1.80 7.20

Potenciometro 3 0.10 0.30

IRFP 9140 0 12.50 0.00

IRFP 250 1 11.69 11.69

Resistencia potencia 2 4.21 8.42

BYW 29-200 1 0.85 0.85

Inductor Acoplado 1 27.10 27.10 Precio de la topología 62.39 Euros. Mano de obra 12.00 Euros. TOTAL 74.39 Euros.


Página 8 de 8

TOPOLOGÍA REDUCTORA

Componente Cantidad Precio

unitario Total (Euros)

BC 337-338 2 0.10 0.20

Condens. electrolítico 5 0.06 0.30

Resistencia 7 0.06 0.42

Diodos Zener 3 0.06 0.18

ICL 8038 1 4.70 4.70

CA 3130 1 1.35 1.35

Condensador Poliester 4 1.80 7.20

Potenciometro 3 0.10 0.30

IRFP 9140 1 12.50 12.50

IRFP 250 0 11.69 0.00

Resistencia potencia 2 4.21 8.42

BYW 29-200 1 0.85 0.85

Inductor Acoplado 1 27.10 27.10 Precio de la topología 63.52 Euros. Mano de obra 12.00 Euros. TOTAL 75.52 Euros.


Página 1 de 2

7. Pliego de condiciones. Manual de usuario. Conectar los prototipos experimentales a la alimentación correcta. A partir de aquí el resultado obtenido en la salida de los convertidores está controlado y puede ser manipulado mediante tres potenciómetros. Dos de ellos, RA y RB, son los encargados de crear la señal triangular gracias al integrado ICL8038, en la cual regulan la pendiente de subida y la de bajada de la señal triangular, variando el valor de la frecuencia. Por tanto como la frecuencia de trabajo es constante, de 20 kHz, dichos potenciometros son regulados inicialmente y por tanto no deben ser manipulados durante el estudio de los diferentes prototipos.

Fig. 7.1 Esquema circuital del ICL8038.


Página 2 de 2

Los valores de los potenciometros son hallados mediante las ecuaciones que se muestran a continuación:

(7.1)

RA= RB = R

En cambio el potenciometro que a continuación aparece, RC, es el utilizado para crear el denominado “Duty-Cycle” (ciclo de trabajo) comparando la anterior señal triangular con una señal de dicho potenciomentro mediante un comparador, el CA3130 apropiado para nuestra frecuencia de trabajo. Con ello se obtiene diferentes tipos de regulaciones según el prototipo manipulado.

Fig. 7.2 Comparador para crear el “Duty-cycle”.

En caso de que se quisiera realizar el prototipo en lazo cerrado una posible solución sería que el valor de Rc además de ser controlado por el usuario dependiera de los valores de tensión de la salida. Con ello se conseguiría una regulación automática. Entonces según el valor de la salida el “Duty-cycle” sería modificado.

RC


Página 1 de 47

Apendice. Anexo A. Resultados Wmaple32. CONVERTIDOR BOOST > Auss := array ([[0,-Dn/L],[Dn/C,-1/(R*C)]]); [ Dn ] [ 0 - ---- ] [ L ] Auss := [ ] [ Dn 1 ] [---- - --- ] [C R C ] > Buss := array ([[1/L*Vg],[0]]); [ Vg ] [---- ] Buss :=[ L ] [ ] [ 0 ] Xss= -Auss^(-1)*Buss > inv := map (simplify, evalm (-Auss^(-1))); [ L C ] [----- - ---- ] [ 2 Dn ] inv := [R Dn ] [ ] [ L ] [---- 0 ] [ Dn ] > Xss := map (simplify, evalm (inv &* Buss)); [ Vg ] [----- ] [ 2 ] Xss := [R Dn ] [ ] [ Vg ] [---- ]


Página 2 de 47

[ Dn ] Modelo en pequeña señal. Gs=V(s)/Vg(s) para D=0; (S1-Auss)*x(s)=Busse*vg(s) > s= array ([[s,0],[0,s]]); [s 0] s = [ ] [0 s] > inv1 := map (simplify,evalm ( s - Auss)); [ Dn ] [ s ---- ] [ L ] inv1 := [ ] [ Dn 1 + s R C] [- ---- --------- ] [ C R C ] > inv2 := map (simplify,evalm (inv1^(-1))); [(1 + s R C) L Dn R C ] [------------- - ------ ] [ %1 %1 ] inv2 := [ ] [ Dn R L s R C L ] [ ------ ------- ] [ %1 %1 ] 2 2 %1 := s L + s L R C + R Dn > Busse := map (simplify, evalm (Buss/Vg)); [1/L] Busse := [ ] [ 0 ]


Página 3 de 47

> Gs := map (simplify, evalm ((inv2 &* Busse)*vg)); [ vg (1 + s R C) ] [ ---------------------- ] [ 2 2 ] [s L + s L R C + R Dn ] Gs := [ ] [ vg Dn R ] [ ---------------------- ] [ 2 2 ] [s L + s L R C + R Dn ] Gs= v(s)/u(s) para vg=0 (S1-Auss)x(s)=K*u(s) k=(A1-A2)XSS+B1ss-B2ss > Adif := array ([[0,1/L],[-1/C,0]]); [ 0 1/L] Adif := [ ] [- 1/C 0 ] > K := map (simplify, evalm (Adif &* Xss)); [ Vg ] [ ---- ] [ L Dn ] K := [ ] [ Vg ] [- ------- ] [ 2 ] [ C R Dn ] > X := map (simplify, evalm ((inv2 &* K)*u)); [ u Vg (2 + s R C) ] [--------------------------- ] [ 2 2 ] [(s L + s L R C + R Dn ) Dn ] X := [ ] [ 2 ] [ u Vg (R Dn - s L) ] [---------------------------- ] [ 2 2 2 ] [(s L + s L R C + R Dn ) Dn ]


Página 4 de 47

Calculo de la impedancia de salida Zo. > Auss := array ([[0,-Dn/L],[Dn/C,-1/(R*C)]]); [ Dn ] [ 0 - ---- ] [ L ] Auss := [ ] [ Dn 1 ] [---- - --- ] [ C R C ] > Buss := array ([[1/L,0],[0,1/C]]); [1/L 0 ] Buss := [ ] [ 0 1/C] Para Vg=U=0: > X := map (simplify, evalm (inv2 &* Buss)); [1 + s R C Dn R] [--------- - ---- ] [ %1 %1 ] X := [ ] [ Dn R s R L ] [ ---- ----- ] [ %1 %1 ] 2 2 %1 := s L + s L R C + R Dn >


Página 5 de 47

CONVERTIDOR BUCK Análisis en regimen estacionario. Xss=-Auss^(-1)*Buss > X:= [I,V]; X := [I, V] > Auss := array ([[0,-1/L],[1/C,-1/(C*R)]]); [ 0 - 1/L] [ ] Auss := [ 1 ] [1/C - ---] [ C R ] > Buss := array ([[D/L*Vg],[0]]); [D Vg] [ ---- ] Buss := [ L ] [ ] [ 0 ] Respuesta en régimen estacionario. > Inv := map (simplify, evalm (-Auss^(-1))); [L/R -C] Inv := [ ] [ L 0 ] > > Xss := map (simplify, evalm (-Auss^(-1)*Buss)); [D Vg] [ ---- ] Xss := [ R ] [ ] [D Vg]


Página 6 de 47

Modelaje en pequeña señal. Gs= V(s)/Vg(s) para u=0; (s1-Auss)X(s)=Busse*Vg(s) donde Busse=Buss/Vg > S1 := array ([[s,0],[0,s]]); [s 0] S1 := [ ] [0 s] > P1 := map (simplify, evalm (S1-Auss)); [ s 1/L ] [ ] P1 := [ s C R + 1] [- 1/C --------- ] [ C R ] > P2 := map (simplify, evalm(P1 ^ (-1))); [ (s C R + 1) L C R ] [------------------ - ------------------ ] [ 2 2 ] [s L C R + s L + R s L C R + s L + R] P2 := [ ] [ R L s C R L ] [------------------ ------------------ ] [ 2 2 ] [s L C R + s L + R s L C R + s L + R ] > Busse := map (simplify, evalm (Buss/Vg)); [D/L] Busse := [ ] [ 0 ] > X := map (simplify, evalm ((P2 &* Busse)*Vg)); [ Vg (s C R + 1) D ] [ ------------------ ] [ 2 ] [s L C R + s L + R] X := [ ] [ Vg R D ] [ ------------------ ] [ 2 ]


Página 7 de 47

[s L C R + s L + R] Modelaje en pequeña señal. Gs= V(s)/U(s) para Vg=0; (s1-Auss)X(s)=K*U(s) donde K=(A1-A2)Xss+B1ss-B2ss > K := map (simplify, evalm (Buss/D)); [ Vg ] [ ---- ] K := [ L ] [ ] [ 0 ] > X := map (simplify, evalm ((P2 &* K)*U(s))); [U(s) (s C R + 1) Vg] [------------------- ] [ 2 ] [s L C R + s L + R ] X := [ ] [ U(s) R Vg ] [------------------ ] [ 2 ] [s L C R + s L + R ] Calculo de la Zout. > Buss := array ([[D/L,0],[0,1/C]]); [D/L 0 ] Buss := [ ] [ 0 1/C] > Y := array ([[0],[ig]]); [0 ] Y := [ ] [ig] > Xs := map (simplify, evalm (P2 &* Buss &* Y)); [ R ig ] [- ------------------ ] [ 2 ] [ s L C R + s L + R] Xs := [ ] [ s R L ig ] [ ------------------ ] [ 2 ]


Página 8 de 47

[ s L C R + s L + R ] CONVERTIDOR TAPPED_BOOST > Auss := array ([[0,-Dn/(L*(N+1))],[Dn/(C*(N+1)),-1/(R*C)]]); [ Dn ] [ 0 - ---------] [ L (N + 1)] Auss := [ ] [ Dn 1 ] [--------- - --- ] [C (N + 1) R C ] > Buss := array ([[(((N*D)+1)/((N+1)*L))*Vg],[0]]); [(N D + 1) Vg] [------------ ] Buss := [ L (N + 1) ] [ ] [ 0 ] Xss= -Auss^(-1)*Buss > inv := map (simplify, evalm (-Auss^(-1))); [ 2 ] [L (N + 1) (N + 1) C] [---------- - ---------] [ 2 Dn ] inv := [ R Dn ] [ ] [(N + 1) L ] [--------- 0 ] [ Dn ] > Xss := map (simplify, evalm (inv &* Buss)); [(N + 1) (N D + 1) Vg] [-------------------- ] [ 2 ] Xss := [ R Dn ] [ ] [ (N D + 1) Vg ] [ ------------ ] [ Dn ]


Página 9 de 47

Modelo en pequeña señal. Gs=V(s)/Vg(s) para D=0; (S1-Auss)*x(s)=Busse*vg(s) > s= array ([[s,0],[0,s]]); [s 0] s = [ ] [0 s] > inv1 := map (simplify,evalm ( s - Auss)); [ Dn ] [ s --------- ] [ L (N + 1) ] inv1 := [ ] [ Dn 1 + s R C] [- --------- --------- ] [ C (N + 1) R C ] > inv2 := map (simplify,evalm (inv1^(-1))); [ 2 ] [ (1 + s R C) L (N + 1) Dn (N + 1) R C] [---------------------- - -------------- ] [ %1 %1 ] inv2 := [ ] [ 2 ] [ Dn (N + 1) R L s R C L (N + 1) ] [ -------------- ---------------- ] [ %1 %1 ] 2 2 2 2 2 %1 := s L N + 2 s L N + s L + s L R C N + 2 s L R C N + s L R C 2 + R Dn > Busse := map (simplify, evalm (Buss/Vg)); [ N D + 1 ] [ --------- ] Busse := [L (N + 1)] [ ] [ 0 ]


Página 10 de 47

> Gs := map (simplify, evalm ((inv2 &* Busse)*vg)); Gs := [ 2 [vg (1 + s R C) (N + 1) (N D + 1)/(s L N + 2 s L N + s L 2 2 2 2 2 ] + s L R C N + 2 s L R C N + s L R C + R Dn )] [ 2 2 2 [vg Dn R (N D + 1)/(s L N + 2 s L N + s L + s L R C N 2 2 2 ] + 2 s L R C N + s L R C + R Dn )] Gs= v(s)/u(s) para vg=0 (S1-Auss)x(s)=K*u(s) k=(A1-A2)XSS+B1ss-B2ss > Adif := array ([[0,1/L],[-1/C,0]]); [ 0 1/L] Adif := [ ] [- 1/C 0 ] > K := map (simplify, evalm (Adif &* Xss)); [ (N D + 1) Vg ] [ ------------ ] [ L Dn ] K := [ ] [ (N + 1) (N D + 1) Vg] [- --------------------] [ 2 ] [ C R Dn ] > X := map (simplify, evalm ((inv2 &* K)*u)); X := [ 2 / 2 [u (N + 1) (N D + 1) Vg (2 + s R C) / ((s L N + 2 s L N + s L [ / 2 2 2 2 2 ]


Página 11 de 47

+ s L R C N + 2 s L R C N + s L R C + R Dn ) Dn)] ] [ 2 2 / [u (N + 1) (N D + 1) Vg (R Dn - s L N - 2 s L N - s L) / (( [ / 2 2 2 2 2 s L N + 2 s L N + s L + s L R C N + 2 s L R C N + s L R C 2 2 ] + R Dn ) Dn )] ] Calculo de la impedancia de salida Zo. > Auss := array ([[0,-Dn/L],[Dn/C,-1/(R*C)]]); [ Dn ] [ 0 - ----] [ L ] Auss := [ ] [ Dn 1 ] [---- - --- ] [ C R C ] > Buss := array ([[1/L,0],[0,1/C]]); [1/L 0 ] Buss := [ ] [ 0 1/C] Para Vg=U=0: > X := map (simplify, evalm (inv2 &* Buss)); [ 2 ] [(1 + s R C) (N + 1) Dn (N + 1) R] [-------------------- - ------------] [ %1 %1 ] X := [ ] [ 2] [ Dn (N + 1) R s R L (N + 1) ] [ ------------ --------------] [ %1 %1 ] 2 2 2 2 2


Página 12 de 47

%1 := s L N + 2 s L N + s L + s L R C N + 2 s L R C N + s L R C 2 + R Dn >


Página 13 de 47

CONVERTIDOR TAPPED_BOOST (A) (Diodo en la mitad de la bobina) > Auss := array ([[0,-Dn/L],[Dn/C,-1/(R*C)]]); [ Dn ] [ 0 - ----] [ L ] Auss := [ ] [ Dn 1 ] [---- - --- ] [ C R C ] > Buss := array ([[(((N*Dn)+1)/((N+1)*L))*Vg],[0]]); [(N Dn + 1) Vg] [-------------] Buss := [ (N + 1) L ] [ ] [ 0 ] Xss= -Auss^(-1)*Buss > inv := map (simplify, evalm (-Auss^(-1))); [ L C ] [----- - ----] [ 2 Dn ] inv := [R Dn ] [ ] [ L ] [---- 0 ] [ Dn ] > Xss := map (simplify, evalm (inv &* Buss)); [(N Dn + 1) Vg] [-------------] [ 2 ] Xss := [R Dn (N + 1)] [ ] [(N Dn + 1) Vg] [-------------] [ Dn (N + 1) ] Modelo en pequeña señal. Gs=V(s)/Vg(s) para D=0; (S1-Auss)*x(s)=Busse*vg(s) > s= array ([[s,0],[0,s]]);


Página 14 de 47

[s 0] s = [ ] [0 s] > inv1 := map (simplify,evalm ( s - Auss)); [ Dn ] [ s ---- ] [ L ] inv1 := [ ] [ Dn 1 + s R C] [- ---- ---------] [ C R C ] > inv2 := map (simplify,evalm (inv1^(-1))); [(1 + s R C) L Dn R C] [------------- - ------] [ %1 %1 ] inv2 := [ ] [ Dn R L s R C L ] [ ------ ------- ] [ %1 %1 ] 2 2 %1 := s L + s L R C + R Dn > Busse := map (simplify, evalm (Buss/Vg)); [N Dn + 1 ] [---------] Busse := [(N + 1) L] [ ] [ 0 ] > Gs := map (simplify, evalm ((inv2 &* Busse)*vg)); [ vg (1 + s R C) (N Dn + 1) ] [--------------------------------] [ 2 2 ] [(s L + s L R C + R Dn ) (N + 1)] Gs := [ ] [ vg Dn R (N Dn + 1) ] [--------------------------------]


Página 15 de 47

[ 2 2 ] [(s L + s L R C + R Dn ) (N + 1)] Gs= v(s)/u(s) para vg=0 (S1-Auss)x(s)=K*u(s) k=(A1-A2)XSS+B1ss-B2ss > Adif := array ([[0,1/L],[-1/C,0]]); [ 0 1/L] Adif := [ ] [- 1/C 0 ] > K := map (simplify, evalm (Adif &* Xss)); [ (N Dn + 1) Vg ] [ ------------- ] [ L Dn (N + 1) ] K := [ ] [ (N Dn + 1) Vg ] [- ---------------] [ 2 ] [ C R Dn (N + 1)] > X := map (simplify, evalm ((inv2 &* K)*u)); [ u (N Dn + 1) Vg (2 + s R C) ] [----------------------------------- ] [ 2 2 ] [(s L + s L R C + R Dn ) Dn (N + 1) ] X := [ ] [ 2 ] [ u (N Dn + 1) Vg (R Dn - s L) ] [------------------------------------] [ 2 2 2 ] [(s L + s L R C + R Dn ) Dn (N + 1)] Calculo de la impedancia de salida Zo. > Auss := array ([[0,-Dn/L],[Dn/C,-1/(R*C)]]); [ Dn ] [ 0 - ----] [ L ] Auss := [ ] [ Dn 1 ] [---- - --- ] [ C R C ]


Página 16 de 47

> Buss := array ([[1/L,0],[0,1/C]]); [1/L 0 ] Buss := [ ] [ 0 1/C] Para Vg=U=0: > X := map (simplify, evalm (inv2 &* Buss)); [1 + s R C Dn R] [--------- - ----] [ %1 %1 ] X := [ ] [ Dn R s R L ] [ ---- ----- ] [ %1 %1 ] 2 2 %1 := s L + s L R C + R Dn


Página 17 de 47

CONVERTIDOR TAPPED_BUCK B Análisis en regimen estacionario. Xss=-Auss^(-1)*Buss > X:= [I,V]; X := [I, V] > Auss := array ([[0,(-D*(N+1)-Dn)/(L*(N+1))],[(D*(N+1)+Dn)/(C*(N+1)),-1/(C*R)]]); [ -D (N + 1) - Dn] [ 0 ---------------] [ L (N + 1) ] Auss := [ ] [D (N + 1) + Dn 1 ] [-------------- - --- ] [ C (N + 1) C R ] > Buss := array ([[D/(L)*Vg],[0]]); [D Vg] [----] Buss := [ L ] [ ] [ 0 ] Respuesta en régimen estacionario. > Inv := map (simplify, evalm (-Auss^(-1))); [ 2 ] [ L (N + 1) C (N + 1) ] [----------------- - ------------] [ 2 D N + D + Dn] Inv := [R (D N + D + Dn) ] [ ] [ L (N + 1) ] [ ------------ 0 ] [ D N + D + Dn ] > > Xss := map (simplify, evalm (-Auss^(-1)*Buss)); [ 2 ]


Página 18 de 47

[ (N + 1) D Vg ] [-----------------] [ 2] Xss := [R (D N + D + Dn) ] [ ] [ (N + 1) D Vg ] [ ------------ ] [ D N + D + Dn ] Modelaje en pequeña señal. Gs= V(s)/Vg(s) para u=0; (s1-Auss)X(s)=Busse*Vg(s) donde Busse=Buss/Vg > S1 := array ([[s,0],[0,s]]); [s 0] S1 := [ ] [0 s] > P1 := map (simplify, evalm (S1-Auss)); [ D N + D + Dn] [ s ------------] [ L (N + 1) ] P1 := [ ] [ D N + D + Dn s C R + 1 ] [- ------------ --------- ] [ C (N + 1) C R ] > P2 := map (simplify, evalm(P1 ^ (-1))); [ 2 ] [ (s C R + 1) L (N + 1) (D N + D + Dn) (N + 1) C R] [ ---------------------- - --------------------------] [ %1 %1 ] P2 := [ ] [ 2 ] [(D N + D + Dn) (N + 1) R L s C R L (N + 1) ] [-------------------------- ---------------- ] [ %1 %1 ] 2 2 2 2 2 %1 := s L C R N + 2 s L C R N + s L C R + s L N + 2 s L N + s L 2 2 2 2 2 + R D N + 2 R D N + 2 R D N Dn + R D + 2 R D Dn + R Dn


Página 19 de 47

> Busse := map (simplify, evalm (Buss/Vg)); [D/L] Busse := [ ] [ 0 ] > X := map (simplify, evalm ((P2 &* Busse)*Vg)); X := [ 2 / 2 2 2 [Vg (s C R + 1) (N + 1) D / (s L C R N + 2 s L C R N [ / 2 2 2 2 2 + s L C R + s L N + 2 s L N + s L + R D N + 2 R D N 2 2 ] + 2 R D N Dn + R D + 2 R D Dn + R Dn )] ] [ 2 2 2 [Vg (D N + D + Dn) (N + 1) R D/(s L C R N + 2 s L C R N 2 2 2 2 2 + s L C R + s L N + 2 s L N + s L + R D N + 2 R D N 2 2 ] + 2 R D N Dn + R D + 2 R D Dn + R Dn )] Modelaje en pequeña señal. Gs= V(s)/U(s) para Vg=0; (s1-Auss)X(s)=K*U(s) donde K=(A1-A2)Xss+B1ss-B2ss > K := map (simplify, evalm (Buss/D)); [ Vg ] [----] K := [ L ] [ ] [ 0 ] > X := map (simplify, evalm ((P2 &* K)*U(s))); X :=


Página 20 de 47

[ 2 / 2 2 2 [U(s) (s C R + 1) (N + 1) Vg / (s L C R N + 2 s L C R N [ / 2 2 2 2 2 + s L C R + s L N + 2 s L N + s L + R D N + 2 R D N 2 2 ] + 2 R D N Dn + R D + 2 R D Dn + R Dn )] ] [ 2 2 2 [U(s) (D N + D + Dn) (N + 1) R Vg/(s L C R N + 2 s L C R N 2 2 2 2 2 + s L C R + s L N + 2 s L N + s L + R D N + 2 R D N 2 2 ] + 2 R D N Dn + R D + 2 R D Dn + R Dn )] Calculo de la Zout. > Buss := array ([[D/L,0],[0,1/C]]); [D/L 0 ] Buss := [ ] [ 0 1/C] > Y := array ([[0],[ig]]); [0 ] Y := [ ] [ig] > Xs := map (simplify, evalm (P2 &* Buss &* Y)); Xs := [ 2 2 2 [- (D N + D + Dn) (N + 1) R ig/(s L C R N + 2 s L C R N 2 2 2 2 2 + s L C R + s L N + 2 s L N + s L + R D N + 2 R D N 2 2 ]


Página 21 de 47

+ 2 R D N Dn + R D + 2 R D Dn + R Dn )] [ 2 / 2 2 2 2 [s R L (N + 1) ig / (s L C R N + 2 s L C R N + s L C R [ / 2 2 2 2 + s L N + 2 s L N + s L + R D N + 2 R D N + 2 R D N Dn 2 2 ] + R D + 2 R D Dn + R Dn )] ] >


Página 22 de 47

CONVERTIDOR TAPPED BUCK C. Análisis en regimen estacionario. Xss=-Auss^(-1)*Buss > X:= [I,V]; X := [I, V] > Auss := array ([[0,(-D*N-Dn*(N+1))/(L*(N+1)*N)],[(D*N+(Dn*(N+1)))/(C*(N+1)*N),-1/(C*R)]]); [ -D N - Dn (N + 1)] [ 0 -----------------] [ L (N + 1) N ] Auss := [ ] [D N + Dn (N + 1) 1 ] [---------------- - --- ] [ C (N + 1) N C R ] > Buss := array ([[D/((N+1)*L)*Vg],[0]]); [ D Vg ] [---------] Buss := [(N + 1) L] [ ] [ 0 ] Respuesta en régimen estacionario. > Inv := map (simplify, evalm (-Auss^(-1))); [ 2 2 ] [ L (N + 1) N C (N + 1) N ] [-------------------- - ---------------] [ 2 D N + Dn N + Dn] Inv := [R (D N + Dn N + Dn) ] [ ] [ L (N + 1) N ] [ --------------- 0 ] [ D N + Dn N + Dn ] > > Xss := map (simplify, evalm (-Auss^(-1)*Buss)); [ 2 ]


Página 23 de 47

[ (N + 1) N D Vg ] [--------------------] [ 2] Xss := [R (D N + Dn N + Dn) ] [ ] [ N D Vg ] [ --------------- ] [ D N + Dn N + Dn ] Modelaje en pequeña señal. Gs= V(s)/Vg(s) para u=0; (s1-Auss)X(s)=Busse*Vg(s) donde Busse=Buss/Vg > S1 := array ([[s,0],[0,s]]); [s 0] S1 := [ ] [0 s] > P1 := map (simplify, evalm (S1-Auss)); [ D N + Dn N + Dn] [ s ---------------] [ L (N + 1) N ] P1 := [ ] [ D N + Dn N + Dn s C R + 1 ] [- --------------- --------- ] [ C (N + 1) N C R ] > P2 := map (simplify, evalm(P1 ^ (-1))); P2 := [ 2 2 ] [(s C R + 1) L (N + 1) N (D N + Dn N + Dn) (N + 1) N C R] [------------------------- , - -------------------------------] [ %1 %1 ] [ 2 2] [(D N + Dn N + Dn) (N + 1) N R L s C R L (N + 1) N ] [------------------------------- , -------------------] [ %1 %1 ] 2 4 2 3 2 2 4 3 %1 := s L N C R + 2 s L N C R + s L C R N + s L N + 2 s L N


Página 24 de 47

2 2 2 2 2 2 + s L N + R D N + 2 R D N Dn + 2 R D N Dn + R Dn N 2 2 + 2 R Dn N + R Dn > Busse := map (simplify, evalm (Buss/Vg)); [ D ] [---------] Busse := [(N + 1) L] [ ] [ 0 ] > X := map (simplify, evalm ((P2 &* Busse)*Vg)); X := [ 2 / 2 4 2 3 [Vg (s C R + 1) (N + 1) N D / (s L N C R + 2 s L N C R [ / 2 2 4 3 2 2 2 + s L C R N + s L N + 2 s L N + s L N + R D N 2 2 2 2 2 ] + 2 R D N Dn + 2 R D N Dn + R Dn N + 2 R Dn N + R Dn )] ] [ 2 4 2 3 [Vg (D N + Dn N + Dn) N R D/(s L N C R + 2 s L N C R 2 2 4 3 2 2 2 + s L C R N + s L N + 2 s L N + s L N + R D N 2 2 2 2 2 ] + 2 R D N Dn + 2 R D N Dn + R Dn N + 2 R Dn N + R Dn )] Modelaje en pequeña señal. Gs= V(s)/U(s) para Vg=0; (s1-Auss)X(s)=K*U(s) donde K=(A1-A2)Xss+B1ss-B2ss > K := map (simplify, evalm (Buss/D)); [ Vg ] [---------]


Página 25 de 47

K := [(N + 1) L] [ ] [ 0 ] > X := map (simplify, evalm ((P2 &* K)*U(s))); X := [ 2 / 2 4 2 3 [U(s) (s C R + 1) (N + 1) N Vg / (s L N C R + 2 s L N C R [ / 2 2 4 3 2 2 2 + s L C R N + s L N + 2 s L N + s L N + R D N 2 2 2 2 2 ] + 2 R D N Dn + 2 R D N Dn + R Dn N + 2 R Dn N + R Dn )] ] [ 2 4 2 3 [U(s) (D N + Dn N + Dn) N R Vg/(s L N C R + 2 s L N C R 2 2 4 3 2 2 2 + s L C R N + s L N + 2 s L N + s L N + R D N 2 2 2 2 2 ] + 2 R D N Dn + 2 R D N Dn + R Dn N + 2 R Dn N + R Dn )] Calculo de la Zout. > Buss := array ([[D/L,0],[0,1/C]]); [D/L 0 ] Buss := [ ] [ 0 1/C] > Y := array ([[0],[ig]]); [0 ] Y := [ ] [ig] > Xs := map (simplify, evalm (P2 &* Buss &* Y)); Xs :=


Página 26 de 47

[ 2 4 2 3 [- (D N + Dn N + Dn) (N + 1) N R ig/(s L N C R + 2 s L N C R 2 2 4 3 2 2 2 + s L C R N + s L N + 2 s L N + s L N + R D N 2 2 2 2 2 ] + 2 R D N Dn + 2 R D N Dn + R Dn N + 2 R Dn N + R Dn )] [ 2 2 / 2 4 2 3 [s R L (N + 1) N ig / (s L N C R + 2 s L N C R [ / 2 2 4 3 2 2 2 + s L C R N + s L N + 2 s L N + s L N + R D N 2 2 2 2 2 ] + 2 R D N Dn + 2 R D N Dn + R Dn N + 2 R Dn N + R Dn )] ] >


Página 27 de 47

Programas Pspice.

CONVERTIDORES BUCK (REDUCTORES DE TENSIÓN)

********************************************************************** ****************CONVERTIDOR BUCK REDUCTOR)*************************** ********************************************************************** VG 1 0 40V S1 1 3 4 0 SMOD L1 3 5 666UH C1 5 0 83UF IC=20 R1 5 0 10 VSW 4 0 PULSE (0 5V 0S 0.1NS 0.1NS 25US 50US) D1 0 3 DIODE .MODEL DIODE D(IS=1.0E-14) .MODEL SMOD VSWITCH(RON=0.01 ROFF=1E+6 VON=5 VOFF=0) .TRAN 100US 18mS 0 100US .PROBE .END


Página 28 de 47

******************************************************************** ***CONVERTIDOR CON INDUCTOR DE BOBINA PARTIDA. INDUCB*************** ******************************************************************** VG 1 0 40V S1 1 4 3 0 SMOD L1 2 4 333.33uH L2 4 5 333.33uH K1 L1 L2 0.999 C1 5 0 83uF R1 5 0 10 VSW 3 0 PULSE (0 5V 0S 0.1NS 0.1NS 16.667US 50uS) D1 0 2 DIODE .MODEL DIODE D(IS=10.0E-14 RS=0) .MODEL SMOD VSWITCH(RON=0.01 ROFF=1E+6 VON=5 VOFF=0) .TRAN 15uS 12mS 0 150uS .PROBE .END


Página 29 de 47

******************************************************************** **CONVERTIDOR CON INDUCTOR DE BOBINA PARTIDA. TRAFOB**************** ******************************************************************** VG 1 0 40V S1 1 4 3 0 SMOD L1 4 5 333.33UH E1 2 4 4 5 1 F1 4 5 VA 1 VA 2 6 0 C1 5 0 83UF R1 5 0 10 VSW 3 0 PULSE (0 5V 0S 0.1NS 0.1NS 16.66US 50US) D1 0 6 DIODE .MODEL DIODE D(IS=10.0E-14 RS=0) .MODEL SMOD VSWITCH(RON=0.01 ROFF=1E+6 VON=5 VOFF=0) .TRAN 15uS 8mS 0 150uS .PROBE .END


Página 30 de 47

********************************************************************** ******CONVERTIDOR CON INDUCTOR DE BOBINA PARTIDA. INDUCC************** ********************************************************************** VG 1 0 40V S1 1 2 3 0 SMOD L1 2 4 333.33uH L2 4 5 333.33uH K1 L1 L2 0.999 C1 5 0 83UF R1 5 0 10 VSW 3 0 PULSE (0 5V 0S 0.1NS 0.1NS 33.33US 50US) D1 0 4 DIODE .MODEL DIODE D(IS=1.0E-14 RS=0) .MODEL SMOD VSWITCH(RON=0.01 ROFF=1E+6 VON=5 VOFF=0) .TRAN 15uS 8mS 0 15uS .PROBE .END


Página 31 de 47

********************************************************************** ******CONVERTIDOR CON INDUCTOR DE BOBINA PARTIDA. TRAFOC************** ********************************************************************** VG 1 0 40V S1 1 2 3 0 SMOD L1 2 4 333.33uH F1 2 4 VA 1 E1 4 6 2 4 1 VA 5 6 0 C1 5 0 83UF R1 5 0 10 VSW 3 0 PULSE (0 5V 0S 0.1NS 0.1NS 33.33US 50US) D1 0 4 DIODE .MODEL DIODE D(IS=1.0E-14 RS=0) .MODEL SMOD VSWITCH(RON=0.01 ROFF=1E+6 VON=5 VOFF=0) .TRAN 10uS 8mS 0 10us .PROBE .END


Página 32 de 47

CONVERTIDORES BOOST (ELEVADORES )

********************************************************************** *******************CONVERTIDOR BOOST (IDEAL)************************** ********************************************************************** VG 1 0 20V S1 2 0 3 0 SMOD L1 1 2 666UH C1 4 0 83UF IC=40 R1 4 0 40 VSW 3 0 PULSE (0 5V 0S 0.1NS 0.1NS 25US 50US) D1 2 4 DIODE .MODEL DIODE D(IS=1.0E-14) .MODEL SMOD VSWITCH(RON=0.01 ROFF=1E+6 VON=5 VOFF=0) .TRAN 100US 30mS 0 100US .PROBE .END


Página 33 de 47

********************************************************************** ******CONVERTIDOR CON INDUCTOR DE BOBINA PARTIDA. INDUC*************** ********************************************************************** VG 1 0 20V S1 2 0 3 0 SMOD L1 1 2 333.33UH L2 2 4 333.33UH K1 L1 L2 0.999 C1 0 5 83UF R1 0 5 40 VSW 3 0 PULSE (0 5V 0S 0.1NS 0.1NS 16.67US 50US) D1 4 5 DIODE .MODEL DIODE D(IS=1.0E-14 RS=0) .MODEL SMOD VSWITCH(RON=0.01 ROFF=1E+6 VON=5 VOFF=0) .TRAN 100US 25mS 0 500US .PROBE .END


Página 34 de 47

********************************************************************** *****CONVERTIDOR CON INDUCTOR DE BOBINA PARTIDA. TRAFO1*************** ********************************************************************** VG 1 0 20V S1 2 0 3 0 SMOD L1 1 2 333.333uH F1 1 2 VA 1 E1 2 6 1 2 1 VA 4 6 0 C1 0 5 83UF R1 0 5 40 VSW 3 0 PULSE (0 5V 0S 0.1NS 0.1NS 16.66US 50US) D1 4 5 DIODE .MODEL DIODE D(IS=1.0E-14 RS=0) .MODEL SMOD VSWITCH(RON=0.01 ROFF=1E+6 VON=5 VOFF=0) .TRAN 100US 25mS 0 500US .PROBE .END


Página 35 de 47

********************************************************************** ******CONVERTIDOR CON INDUCTOR DE BOBINA PARTIDA. INDUCA************** ********************************************************************** VG 1 0 20V S1 4 0 3 0 SMOD L1 1 2 333.33uH L2 2 4 333.33uH K1 L1 L2 0.999 C1 0 5 83UF R1 0 5 40 VSW 3 0 PULSE (0 5V 0S 0.1NS 0.1NS 33.33US 50US) D1 2 5 DIODE .MODEL DIODE D(IS=1.0E-14 RS=0) .MODEL SMOD VSWITCH(RON=0.01 ROFF=1E+6 VON=5 VOFF=0) .TRAN 150US 25mS 0 150US .PROBE .END


Página 36 de 47

********************************************************************** ***CONVERTIDOR CON INDUCTOR DE BOBINA PARTIDA. TRAFOA***************** ********************************************************************** VG 1 0 20V S1 4 0 3 0 SMOD L1 1 2 333.33uH F1 1 2 VA 1 E1 2 6 1 2 1 VA 4 6 0 C1 0 5 83UF R1 0 5 40 VSW 3 0 PULSE (0 5V 0S 0.1NS 0.1NS 33.33US 50US) D1 2 5 DIODE .MODEL DIODE D(IS=1.0E-14 RS=0) .MODEL SMOD VSWITCH(RON=0.01 ROFF=1E+6 VON=5 VOFF=0) .TRAN 150US 25mS 0 150US .PROBE .END


Página 37 de 47

Programas Matlab. %Cálculo del diagrama de bode y polo cero respecto %a un escalón unitario. %CONVERTIDOR BUCK R=10; C=83E-6; L=666.66E-6; D=1/2; CTE=1/(L*C); NUM=[CTE]; DEN=[1 1/(R*C) 1/(L*C)]; figure(1); step(NUM,DEN) figure(2); w=logspace(2,4); [margen,fase,w]=bode(NUM,DEN,w) margin(margen,fase,w) figure(3); rlocus(NUM,DEN) damp (DEN) end%


Página 38 de 47

%Cálculo del diagrama de bode y polo cero respecto %a un escalón unitario. %CONVERTIDOR BOOST R=40; C=83E-6; L=666.66E-6; D=0.5; CTE=(1-D)/(L*C); NUM=[CTE]; DEN=[1 1/(R*C) (1-D)^2/(L*C)]; figure(1); step(NUM,DEN); figure(2); w=logspace(2,4); [margen,fase,w]=bode(NUM,DEN,w); margin(margen,fase,w); figure(3); rlocus(NUM,DEN); damp (DEN); end


Página 39 de 47

%Cálculo del diagrama de bode y polo cero respecto %a un escalón unitario. %CONVERTIDOR TAPPED-BUCK1 R=10; C=83E-6; L=333.33E-6; D=1/3; CTE=R*D*(D+1)*2; NUM=[CTE]; DEN=[L*R*C*4 L*4 R*(D+1)^2]; figure(1); step(NUM,DEN) figure(2); w=logspace(2,4); [margen,fase,w]=bode(NUM,DEN,w) margin(margen,fase,w) figure(3); rlocus(NUM,DEN) damp (DEN) end%


Página 40 de 47

%Cálculo del diagrama de bode y polo cero respecto %a un escalón unitario. %CONVERTIDOR TAPPED-BUCK2 R=10; C=83E-6; L=333.33E-6; D=2/3; CTE=R*D*(2-D); NUM=[CTE]; DEN=[L*R*C*4 L*4 R*(2-D)^2]; figure(1); step(NUM,DEN) figure(2); w=logspace(2,4); [margen,fase,w]=bode(NUM,DEN,w) margin(margen,fase,w) figure(3); rlocus(NUM,DEN) damp (DEN) end%


Página 41 de 47

%Cálculo del diagrama de bode y polo cero respecto %a un escalón unitario. %CONVERTIDOR TAPPED-BOOST1 R=40; C=83E-6; L=333.33E-6; D=1/3; CTE=(1-D)*R*(D+1); NUM=[CTE]; DEN=[L*R*C*4 L*4 R*(1-D)^2]; figure(1); step(NUM,DEN) figure(2); w=logspace(2,4); [margen,fase,w]=bode(NUM,DEN,w) margin(margen,fase,w) figure(3); rlocus(NUM,DEN) %Coeficiente de amortiguamiento y frecuencia natural de oscilación damp (DEN) end%


Página 42 de 47

%Cálculo del diagrama de bode y polo cero respecto %a un escalón unitario. %CONVERTIDOR TAPPED-BOOST2 R=40; C=83E-6; L=333.33E-6; D=2/3; CTE=(1-D)*R*(1-D+1); NUM=[CTE]; DEN=[L*R*C*2 L*2 R*(1-D)^2*2]; figure(1); step(NUM,DEN) figure(2); w=logspace(2,4); [margen,fase,w]=bode(NUM,DEN,w) margin(margen,fase,w) figure(3); rlocus(NUM,DEN) damp (DEN) end%


Página 43 de 47

Anexo B. Realización bobinas acopladas. El cálculo que a continuación se realiza se obtiene a partir de sobrevaloraciones escogidas. O sea, que para evitar la saturación del núcleo del inductor acoplado hemos elegido un valor máximo de corriente que circula por dicho inductor de 5 Amperios. El valor de las diferentes bobinas del inductor es de 333 µH. A partir de aquí se observa una tabla de núcleos que pueden ser utilizados:


Página 44 de 47

Dependiendo del valor de las inductancias L1 , L2, de la corriente nominal IM y la separación del entrehierro denominado Gap escogido :

mm.)separación(Gap

AI

H.LL

H.L

M

TOTAL

505

33333322333333

≈≈

⋅=⋅==

µµ

Por tanto:

JJ.IL MTOTAL332 1020106616 −− ⋅≈⋅=⋅

Observando en la anterior tabla de núcleos el obtenido es: “EE 65 / 66 / 27 ” Las características del núcleo elegido se muestran a continuación:


Página 45 de 47

Para la obtención del número de espiras del inductor acoplado se basa en la siguiente ecuación:

2NAL L ⋅= donde

→→

→

espirasdeºNN

)nH(vueltas/ainductanciA

)H(bobinavalorL

L 1000µ

donde el valor de AL se obtiene de la tabla anterior a partir del entrehierro elegido (Airgap = 0.5mm). Entonces:

espiras..

A

LN

L1424513

101900

10333339

3≈=

⋅⋅

== −

−

El tamaño elegido del hilo según el material del laboratorio se consideró el más conveniente el hilo de 0.28 mm de diámetro. Se sabe que en todo hilo el paso de corriente se efectúa solo por cierto diámetro. Nunca circula a través de todo el hilo. Por eso es mejor unir varios hilos de diametros menores. Con ello obtenemos una mayor área efectiva de paso de corriente. En la tabla siguiente se muestran una seríe de caracteristicas según el diámetro de hilo elegido:


Página 46 de 47

Según el hilo escogido de 0.28 mm de diámetro, la intensidad que circula por cada uno es de 0.154 A por tanto:

vueltas_..A.

Ivueltas_ºn TOTAL 334632

15405

1540≈===


Página 47 de 47

Anexo C. Archivos PDF.

©2000 Fairchild Semiconductor International Rev. A, February 2000

BD

135/137/139

1 TO-126

NPN Epitaxial Silicon Transistor

Absolute Maximum Ratings TC=25°C unless otherwise noted

Electrical Characteristics TC=25°C unless otherwise noted

hFE Classification

Symbol Parameter Value Units

VCBO Collector-Base Voltage : BD135 : BD137 : BD139

45 60 80

VVV

VCEO Collector-Emitter Voltage : BD135 : BD137 : BD139

45 60 80

VVV

VEBO Emitter-Base Voltage 5 V

IC Collector Current (DC) 1.5 A

ICP Collector Current (Pulse) 3.0 A

IB Base Current 0.5 A

PC Collector Dissipation (TC=25°C) 12.5 W

PC Collector Dissipation (Ta=25°C) 1.25 W

TJ Junction Temperature 150 °C TSTG Storage Temperature - 55 ~ 150 °C

Symbol Parameter Test Condition Min. Typ. Max. Units

VCEO(sus) Collector-Emitter Sustaining Voltage: BD135: BD137: BD139

IC = 30mA, IB = 0 456080

VVV

ICBO Collector Cut-off Current VCB = 30V, IE = 0 0.1 µA

IEBO Emitter Cut-off Current VEB = 5V, IC = 0 10 µA

hFE1 hFE2

hFE3

DC Current Gain : ALL DEVICE: ALL DEVICE: BD135: BD137, BD139

VCE = 2V, IC = 5mAVCE = 2V, IC = 0.5AVCE = 2V, IC = 150mA

25254040

250160

VCE(sat) Collector-Emitter Saturation Voltage IC = 500mA, IB = 50mA 0.5 V

VBE(on) Base-Emitter ON Voltage VCE = 2V, IC = 0.5A 1 V

Classification 6 10 16

hFE3 40 ~ 100 63 ~ 160 100 ~ 250

BD135/137/139

Medium Power Linear and Switching Applications• Complement to BD136, BD138 and BD140 respectively

1. Emitter 2.Collector 3.Base

©2000 Fairchild Semiconductor International

BD

135/137/139

Rev. A, February 2000

Typical Characteristics

Figure 1. DC current Gain Figure 2. Collector-Emitter Saturation Voltage

Figure 3. Base-Emitter Voltage Figure 4. Safe Operating Area

Figure 5. Power Derating

10 100 10000

10

20

30

40

50

60

70

80

90

100VCE = 2V

hF

E,

DC

CU

RR

EN

T G

AIN

IC[mA], COLLECTOR CURRENT

1E-3 0.01 0.1 1 100

50

100

150

200

250

300

350

400

450

500

I C =

10

I B

I C =

20

IB

VC

E(s

at)[

mV

], S

AT

UR

AT

ION

VO

LTA

GE

IC[A], COLLECTOR CURRENT

1E-3 0.01 0.1 1 100.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

VBE(on)

VCE = 5V

VBE(sat)

IC = 10 IB

VB

E[V

], B

AS

E-E

MIT

TE

R V

OL

TA

GE

IC[A], COLLECTOR CURRENT

1 10 1000.01

0.1

1

10

BD

13

9B

D1

37

BD

13

5

10us

100us

1ms

DC

IC MAX. (Pulsed)

IC MAX. (Continuous)

I C

[A],

CO

LL

EC

TO

R C

UR

RE

NT

VCE[V], COLLECTOR-EMITTER VOLTAGE

0 25 50 75 100 125 150 1750.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

20.0

PC[W

], P

OW

ER

DIS

SIP

AT

ION

TC[oC], CASE TEMPERATURE

Package Demensions

©2000 Fairchild Semiconductor International Rev. A, February 2000

BD

135/137/139

Dimensions in Millimeters

3.25 ±0.208.00 ±0.30

ø3.20 ±0.10

0.75 ±0.10

#1

0.75 ±0.10

2.28TYP[2.28±0.20]

2.28TYP[2.28±0.20]

1.60 ±0.10

11

.00

±0

.20

3.9

0 ±

0.1

0

14

.20

MA

X

16

.10

±0

.20

13

.06

±0

.30

1.75 ±0.20

(0.50)(1.00)

0.50+0.10–0.05

TO-126

©2000 Fairchild Semiconductor International Rev. E

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and isnot intended to be an exhaustive list of all such trademarks.

ACEx™Bottomless™CoolFET™CROSSVOLT™E2CMOS™FACT™FACT Quiet Series™FAST®

FASTr™GTO™

HiSeC™ISOPLANAR™MICROWIRE™POP™PowerTrench®

QFET™QS™Quiet Series™SuperSOT™-3SuperSOT™-6

SuperSOT™-8SyncFET™TinyLogic™UHC™VCX™

DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANYPRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANYLIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTORINTERNATIONAL.As used herein:

1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body,or (b) support or sustain life, or (c) whose failure to performwhen properly used in accordance with instructions for useprovided in the labeling, can be reasonably expected toresult in significant injury to the user.

2. A critical component is any component of a life supportdevice or system whose failure to perform can bereasonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design

This datasheet contains the design specifications forproduct development. Specifications may change inany manner without notice.

Preliminary First Production This datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to makechanges at any time without notice in order to improvedesign.

No Identification Needed Full Production This datasheet contains final specifications. FairchildSemiconductor reserves the right to make changes atany time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a productthat has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.

1Motorola Bipolar Power Transistor Device Data

!

. . . designed for use as audio amplifiers and drivers utilizing complementary or quasicomplementary circuits.

• DC Current Gain — hFE = 40 (Min) @ IC = 0.15 Adc• BD 136, 138, 140 are complementary with BD 135, 137, 139

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




MAXIMUM RATINGS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Rating

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

Symbol

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

Type

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Value

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Unit






Collector–Emitter Voltage

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

VCEO

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

BD 136BD 138BD 140

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

456080

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

VdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ






Collector–Base Voltage

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

VCBO

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

BD 136BD 138BD 140

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

4560100

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ





Emitter–Base Voltage

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

VEBO

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

5

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ





Collector Current

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

IC

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

1.5

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

AdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Base Current

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

IB

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

0.5

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

AdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Total Device Dissipation@ TA = 25CDerate above 25C

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

PD

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

1.2510

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

WattsmW/C






Total Device Dissipation @ TC = 25CDerate above 25C

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

PD

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

12.5100

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

WattmW/C






Operating and Storage JunctionTemperarture Range

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

TJ, Tstg

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

–55 to +150

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

CÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




THERMAL CHARACTERISTICS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Characteristic

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

Max

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Unit





Thermal Resistance, Junction to Case

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

θJC

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

10

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

C/W





Thermal Resistance, Junction to Ambient

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

θJA

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎ

100

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

C/W

SEMICONDUCTOR TECHNICAL DATA

Order this documentby BD136/D

Motorola, Inc. 1995

1.5 AMPEREPOWER TRANSISTORS

PNP SILICON45, 60, 80 VOLTS

10 WATTS

CASE 77–08TO–225AA TYPE

REV 7

2 Motorola Bipolar Power Transistor Device Data





ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Characteristic

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Symbol

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Type

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Min

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Max

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

Unit







Collector–Emitter Sustaining Voltage*(IC = 0.03 Adc, IB = 0)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

BVCEO

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

BD 136BD 138BD 140

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

456080

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

———

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

VdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ






Collector Cutoff Current(VCB = 30 Vdc, IE = 0)(VCB = 30 Vdc, IE = 0, TC = 125 C)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ICBO

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

——

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

0.110

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

µAdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Emitter Cutoff Current(VBE = 5.0 Vdc, IC = 0)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

IEBO

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

10

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

µAdc









DC Current Gain(IC = 0.005 A, VCE = 2 V) ALL

(IC = 0.15 A, VCE = 2 V) ALLBD140–10

(IC = 0.5 A, VCE = 2 V)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

hFE*

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

2540

6325

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—250

160—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—






Collector–Emitter Saturation Voltage*(IC = 0.5 Adc, IB = 0.05 Adc)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

VCE(sat)*

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

0.5

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

VdcÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ




Base–Emitter On Voltage*(IC = 0.5 Adc, VCE = 2.0 Vdc)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

VBE(on)*

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

1

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

Vdc

* Pulse Test: Pulse Width 300 µs, Duty Cycle 2.0%.

BD136BD138BD140

TJ = 125°C dc

5 ms 0.5 ms0.1 ms

10

1

Figure 1. Active–Region Safe Operating Area

VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)

5.0

2.0

1.0

0.5

0.012 5 10 20 8050

0.1

0.05

I C, C

OLL

ECTO

R C

UR

REN

T (A

MP)

0.02

0.2

3Motorola Bipolar Power Transistor Device Data

PACKAGE DIMENSIONS

CASE 77–08TO–225AA TYPE

ISSUE V

STYLE 1:PIN 1. EMITTER

2. COLLECTOR3. BASE

NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.

–B–

–A–M

K

F C

Q

H

VG

S

D

JR

U

1 32

2 PL

MAM0.25 (0.010) B M

MAM0.25 (0.010) B M

DIM MIN MAX MIN MAXMILLIMETERSINCHES

A 0.425 0.435 10.80 11.04B 0.295 0.305 7.50 7.74C 0.095 0.105 2.42 2.66D 0.020 0.026 0.51 0.66F 0.115 0.130 2.93 3.30G 0.094 BSC 2.39 BSCH 0.050 0.095 1.27 2.41J 0.015 0.025 0.39 0.63K 0.575 0.655 14.61 16.63M 5 TYP 5 TYPQ 0.148 0.158 3.76 4.01R 0.045 0.055 1.15 1.39S 0.025 0.035 0.64 0.88U 0.145 0.155 3.69 3.93V 0.040 ––– 1.02 –––

4 Motorola Bipolar Power Transistor Device Data

How to reach us:USA / EUROPE: Motorola Literature Distribution; JAPAN : Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: [email protected] – TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in differentapplications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola doesnot convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components insystems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure ofthe Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any suchunintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmlessagainst all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

BD136/D

◊

Features• Plastic package has Underwriters Laboratory

Flammability Classification 94V-0• Glass passivated chip junction• Low power loss • Low leakage current• High surge current capability• Superfast recovery time for high efficiency

Mechanical DataCase: JEDEC TO-220AC, ITO-220AC & TO-263ABmolded plastic bodyTerminals: Plated leads, solderable per MIL-STD-750, Method 2026High temperature soldering in accordance withCECC 802 / Reflow guaranteedPolarity: As markedMounting Position: AnyMounting Torque: 10 in-lbs maximumWeight: approx. 0.05 ounce, 1.35 grams

BYW29, BYWF29, BYWB29 SeriesUltrafast RectifiersReverse Voltage 50 to 200V

Forward Current 8.0AReverse Recovery Time 25ns

10/17/00

0.08(2.032)

0.04(1.016)

0.24(6.096)

0.42(10.66)

0.63(17.02)

0.12(3.05)

0.33(8.38)

Mounting Pad Layout TO-263AB

0.380 (9.65) 0.411 (10.45)

0.320 (8.13) 0.360 (9.14)

0.591 (15.00)

0.624 (15.85)

1 2

0.245 (6.22) MIN

K

0.027 (0.686)

0.037 (0.940)

0.105 (2.67)

0.095 (2.41)0.205 (5.20)

0.195 (4.95)

K

0.160 (4.06)

0.190 (4.83)

0.045 (1.14)

0.055 (1.40)

0.021 (0.53) 0.014 (0.36)

0.110 (2.79)

0.140 (3.56)

0.090 (2.29)

0.110 (2.79)

0.047 (1.19)

0.055 (1.40)

PIN 1

PIN 2 K - HEATSINK

0-0.01 (0-0.254)

0.060 (1.52)

0.405 (10.27)0.383 (9.72)

0.191 (4.85)0.171 (4.35)

0.600 (15.5)0.580 (14.5)

0.560 (14.22)0.530 (13.46)

0.037 (0.94)0.027 (0.69)

0.140 (3.56)0.130 (3.30)

0.350 (8.89)0.330 (8.38)

0.188 (4.77)0.172 (4.36)

0.110 (2.80)0.100 (2.54)

0.131 (3.39)0.122 (3.08)

0.110 (2.80)0.100 (2.54)

0.022 (0.55)0.014 (0.36)0.205 (5.20)

0.195 (4.95)

1 2PIN

DIA.

PIN 1

PIN 2

0.676 (17.2)0.646 (16.4)

ITO-220AC (BYWF29 Series)

0.154 (3.91)

0.148 (3.74)DIA.

0.113 (2.87)0.103 (2.62)

0.185 (4.70)

0.175 (4.44)

0.055 (1.39)0.045 (1.14)

0.145 (3.68)0.135 (3.43)

0.350 (8.89)0.330 (8.38)

0.160 (4.06)

0.140 (3.56)

0.037 (0.94)0.027 (0.68)

0.205 (5.20)0.195 (4.95)

0.560 (14.22)0.530 (13.46)

0.022 (0.56)0.014 (0.36)

0.110 (2.79)0.100 (2.54)

1 2 1.148 (29.16)1.118 (28.40)

0.105 (2.67)

0.095 (2.41)

0.410 (10.41)0.390 (9.91)

0.635 (16.13)

0.625 (15.87)

0.603 (15.32)0.573 (14.55)

PIN

0.415 (10.54) MAX.

PIN 1

PIN 2 CASE

0.370 (9.40)0.360 (9.14)

TO-220AC (BYW29 Series)

Dimensions in inches and (millimeters)

TO-263AB (BYWB29 Series)

Maximum Ratings (TC = 25°C unless otherwise noted)

Parameter Symbol BYW29-50 BYW29-100 BYW29-150 BYW29-200 Unit

Maximum repetitive peak reverse voltage VRRM 50 100 150 200 V

Maximum RMS voltage VRMS 35 70 105 140 V

Maximum DC blocking voltage VDC 50 100 150 200 V

Maximum average forward rectified current at TC = 105°C IF(AV) 8.0 A

Peak forward surge current 8.3ms single half sine-wavesuperimposed on rated load (JEDEC Method) per leg IFSM 100 A

Operating and storage temperature range TJ, TSTG –65 to +150 °C

RMS Isolation voltage (BYWF type only) from terminals 4500 (1)

to heatsink with t = 1.0 second, RH ≤ 30%VISOL 3500 (2) V

1500 (3)

Electrical Characteristics (TC = 25°C unless otherwise noted)

Parameter Symbol BYW29-50 BYW29-100 BYW29-150 BYW29-200 Unit

Maximum instantaneous forward IF = 20A, TJ = 25°C 1.3voltage at: (4) IF = 8.0A, TJ =150°C VF 0.8 V

Maximum DC reverse current TC=25°C 10at rated DC blocking voltage TC=100°C IR 500 µA

Maximum reverse recovery time at IF = 1A, VR = 30V,di/dt = 100A/µs, Irr = 10% IRM

trr 25 ns

Typical junction capacitance at 4V, 1MHz CJ 45 pF

Thermal Characteristics (TC = 25°C unless otherwise noted)

Parameter Symbol BYW BYWF BYWB Unit

Typical thermal resistance from junction to case per leg RΘJC TBD TBD TBD °C/W

Notes:(1) Clip mounting (on case), where lead does not overlap heatsink with 0.110” offset(2) Clip mounting (on case), where leads do overlap heatsink(3) Screw mounting with 4-40 screw, where washer diameter is ≤ 4.9mm (0.19”)(4) Pulse test: 300µs pulse width, 1% duty cycle

BYW29, BYWF29, BYWB29 SeriesUltrafast Rectifiers

BYW29, BYWF29, BYWB29 SeriesUltrafast Rectifiers

Ratings and Characteristic Curves (TA = 25°C unless otherwise noted)

0

20

40

60

80

100

1 10010

Fig. 2 – Maximum Non-Repetitive PeakForward Surge Current

Pea

k F

orw

ard

Sur

ge C

urre

nt (

A)

Number of Cycles at 50 HZ

0

6.0

8.0

10.0

0 25 50 75 100 125 150

Fig. 1 – Maximum Forward Current Derating Curve

Ave

rage

For

war

d R

ectif

ied

Cur

rent

(A

)

Case Temperature (°C)

0.4 0.6 0.8 1.0 1.2

Instantaneous Forward Voltage (V)

Fig. 3 – Typical Instantaneous Forward Characteristics

0 20 6040 10080

Fig. 4 – Typical Reverse Leakage Characteristics

Inst

anta

neou

s R

ever

se L

eaka

ge C

urre

nt

(µA

)

Percent of Rated Peak Reverse Voltage (%)

4.0

2.0

Resistive or Inductive Load

0.01

0.1

10

1

80

Inst

anta

neou

s F

orw

ard

Cur

rent

(A

)

TJ = 125°C

TJ = 25°C

Reverse Voltage (V)

Junc

tion

Cap

acita

nce

(pF

)

0.1 1 10 100

40

30

50

60

70

80

20

0.01

0.1

10

1

100

TJ = 100°C

Fig. 5 – Typical Junction Capacitance

1

CA3130, CA3130A

15MHz, BiMOS Operational Amplifier withMOSFET Input/CMOS Output

CA3130A and CA3130 are op amps that combine theadvantage of both CMOS and bipolar transistors.

Gate-protected P-Channel MOSFET (PMOS) transistors areused in the input circuit to provide very-high-inputimpedance, very-low-input current, and exceptional speedperformance. The use of PMOS transistors in the input stageresults in common-mode input-voltage capability down to0.5V below the negative-supply terminal, an importantattribute in single-supply applications.

A CMOS transistor-pair, capable of swinging the outputvoltage to within 10mV of either supply-voltage terminal (atvery high values of load impedance), is employed as theoutput circuit.

The CA3130 Series circuits operate at supply voltagesranging from 5V to 16V, (±2.5V to ±8V). They can be phasecompensated with a single external capacitor, and haveterminals for adjustment of offset voltage for applicationsrequiring offset-null capability. Terminal provisions are alsomade to permit strobing of the output stage.

The CA3130A offers superior input characteristics overthose of the CA3130.

PinoutsCA3130, CA3130A

(PDIP, SOIC)TOP VIEW

CA3130, CA3130A(METAL CAN)

TOP VIEW

Features

• MOSFET Input Stage Provides:- Very High ZI = 1.5 TΩ (1.5 x 1012Ω) (Typ)- Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation

. . . . . . . . . . . . . . . . . . . . . = 2pA (Typ) at 5V Operation• Ideal for Single-Supply Applications

• Common-Mode Input-Voltage Range IncludesNegative Supply Rail; Input Terminals can be Swung 0.5VBelow Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either (orboth) Supply Rails

Applications

• Ground-Referenced Single Supply Amplifiers

• Fast Sample-Hold Amplifiers

• Long-Duration Timers/Monostables

• High-Input-Impedance Comparators(Ideal Interface with Digital CMOS)

• High-Input-Impedance Wideband Amplifiers

• Voltage Followers (e.g. Follower for Single-Supply D/AConverter)

• Voltage Regulators (Permits Control of Output VoltageDown to 0V)

• Peak Detectors

• Single-Supply Full-Wave Precision Rectifiers

• Photo-Diode Sensor Amplifiers

OFFSET

INV.

NON-INV.

V-

1

2

3

4

8

7

6

5

STROBE

V+

OUTPUT

OFFSET

-+

NULL

INPUT

INPUT

NULL

TAB

OUTPUTINV.

V- AND CASE

OFFSET

NON-INV.

V+

OFFSET

2

4

6

1

3

7

5

8

-+

STROBE

PHASECOMPENSATION

NULLINPUT

INPUT

NULL

Ordering Information

PART NO.(BRAND)

TEMP.RANGE

(oC) PACKAGEPKG.NO.

CA3130AE -55 to 125 8 Ld PDIP E8.3

CA3130AM(3130A)

-55 to 125 8 Ld SOIC M8.15

CA3130AM96(3130A)

-55 to 125 8 Ld SOICTape and Reel

M8.15

CA3130AT -55 to 125 8 Pin Metal Can T8.C

CA3130E -55 to 125 8 Ld PDIP E8.3

CA3130M(3130)

-55 to 125 8 Ld SOIC M8.15

CA3130M96(3130)

-55 to 125 8 Ld SOICTape and Reel

M8.15

CA3130T -55 to 125 8 Pin Metal Can T8.C

Data Sheet September 1998 File Number 817.4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

2

Absolute Maximum Ratings Thermal InformationDC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16VDifferential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8VDC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mAOutput Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite

Operating ConditionsTemperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC

Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/ASOIC Package . . . . . . . . . . . . . . . . . . . 160 N/AMetal Can Package . . . . . . . . . . . . . . . 170 85

Maximum Junction Temperature (Metal Can Package) . . . . . . .175oCMaximum Junction Temperature (Plastic Package) . . . . . . . .150oCMaximum Storage Temperature Range . . . . . . . . . . -65oC to 150oCMaximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Short circuit may be applied to ground or to either supply.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

PARAMETER SYMBOLTEST

CONDITIONS

CA3130 CA3130A

UNITSMIN TYP MAX MIN TYP MAX

Input Offset Voltage |VIO| VS = ±7.5V - 8 15 - 2 5 mV

Input Offset VoltageTemperature Drift

∆VIO/∆T - 10 - - 10 - µV/oC

Input Offset Current |IIO| VS = ±7.5V - 0.5 30 - 0.5 20 pA

Input Current II VS = ±7.5V - 5 50 - 5 30 pA

Large-Signal Voltage Gain AOL VO = 10VP-PRL = 2kΩ

50 320 - 50 320 - kV/V

94 110 - 94 110 - dB

Common-ModeRejection Ratio

CMRR 70 90 - 80 90 - dB

Common-Mode InputVoltage Range

VICR 0 -0.5 to 12 10 0 -0.5 to 12 10 V

Power-SupplyRejection Ratio

∆VIO/∆VS VS = ±7.5V - 32 320 - 32 150 µV/V

Maximum Output Voltage VOM+ RL = 2kΩ 12 13.3 - 12 13.3 - V

VOM- RL = 2kΩ - 0.002 0.01 - 0.002 0.01 V

VOM+ RL = ∞ 14.99 15 - 14.99 15 - V

VOM- RL = ∞ - 0 0.01 - 0 0.01 V

Maximum Output Current IOM+ (Source) at VO = 0V 12 22 45 12 22 45 mA

IOM- (Sink) at VO = 15V 12 20 45 12 20 45 mA

Supply Current I+ VO = 7.5V,RL = ∞

- 10 15 - 10 15 mA

I+ VO = 0V,RL = ∞

- 2 3 - 2 3 mA

CA3130, CA3130A

3

Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oCUnless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONSCA3130,CA3130A UNITS

Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or4 and 1

±22 mV

Input Resistance RI 1.5 TΩ

Input Capacitance CI f = 1MHz 4.3 pF

Equivalent Input Noise Voltage eN BW = 0.2MHz, RS = 1MΩ(Note 3)

23 µV

Open Loop Unity Gain Crossover Frequency(For Unity Gain Stability ≥47pF Required.) fT

CC = 0 15 MHz

CC = 47pF 4 MHz

Slew Rate: SR

CC = 0 30 V/µsOpen Loop

Closed Loop CC = 56pF 10 V/µs

Transient Response: CC = 56pF,CL = 25pF,RL = 2kΩ(Voltage Follower)

0.09 µsRise Time tr

Overshoot OS 10 %

Settling Time (To <0.1%, VIN = 4VP-P) tS 1.2 µs

NOTE:

3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.

Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = 25oCUnless Otherwise Specified (Note 4)

PARAMETER SYMBOL TEST CONDITIONS CA3130 CA3130A UNITS

Input Offset Voltage VIO 8 2 mV

Input Offset Current IIO 0.1 0.1 pA

Input Current II 2 2 pA

Common-Mode Rejection Ratio CMRR 80 90 dB

Large-Signal Voltage Gain AOL VO = 4VP-P, RL = 5kΩ 100 100 kV/V

100 100 dB

Common-Mode Input Voltage Range VICR 0 to 2.8 0 to 2.8 V

Supply Current I+ VO = 5V, RL = ∞ 300 300 µA

VO = 2.5V, RL = ∞ 500 500 µA

Power Supply Rejection Ratio ∆VIO/∆V+ 200 200 µV/V

NOTE:

4. Operation at 5V is not recommended for temperatures below 25oC.

CA3130, CA3130A

4

Schematic Diagram

Application Information

Circuit DescriptionFigure 1 is a block diagram of the CA3130 Series CMOSOperational Amplifiers. The input terminals may be operateddown to 0.5V below the negative supply rail, and the outputcan be swung very close to either supply rail in manyapplications. Consequently, the CA3130 Series circuits areideal for single-supply operation. Three Class A amplifierstages, having the individual gain capability and currentconsumption shown in Figure 1, provide the total gain of theCA3130. A biasing circuit provides two potentials forcommon use in the first and second stages. Terminal 8 canbe used both for phase compensation and to strobe theoutput stage into quiescence. When Terminal 8 is tied to thenegative supply rail (Terminal 4) by mechanical or electricalmeans, the output potential at Terminal 6 essentially rises tothe positive supply-rail potential at Terminal 7. This conditionof essentially zero current drain in the output stage under thestrobed “OFF” condition can only be achieved when the

ohmic load resistance presented to the amplifier is very high(e.g.,when the amplifier output is used to drive CMOS digitalcircuits in Comparator applications).

Input StageThe circuit of the CA3130 is shown in the schematic diagram.It consists of a differential-input stage using PMOS field-effecttransistors (Q6, Q7) working into a mirror-pair of bipolartransistors (Q9, Q10) functioning as load resistors togetherwith resistors R3 through R6. The mirror-pair transistors alsofunction as a differential-to-single-ended converter to providebase drive to the second-stage bipolar transistor (Q11). Offsetnulling, when desired, can be effected by connecting a100,000Ω potentiometer across Terminals 1 and 5 and thepotentiometer slider arm to Terminal 4. Cascade-connectedPMOS transistors Q2, Q4 are the constant-current source forthe input stage. The biasing circuit for the constant-currentsource is subsequently described. The small diodes D5

3

2

1 8 4

6

7

Q1 Q2

Q4

D1

D2

D3

D4

Q3

Q5

D5 D6 D7 D8

Q9 Q10

Q6 Q7

5

Z18.3V

INPUT STAGE

R31kΩ

R41kΩ

R61kΩ

R51kΩ

NON-INV.INPUT

INV.-INPUT+

-

R1

40kΩ

5kΩ

R2

BIAS CIRCUITCURRENT SOURCE FOR “CURRENT SOURCE

LOAD” FOR Q11Q6 AND Q7

V+

OUTPUT

OUTPUTSTAGE Q8

Q12

V-

Q11

SECONDSTAGE

OFFSET NULL COMPENSATION STROBING

(NOTE 5)

NOTE:

5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.

CA3130, CA3130A

5

through D8 provide gate-oxide protection against high-voltagetransients, including static electricity during handling for Q6and Q7.

Second-StageMost of the voltage gain in the CA3130 is provided by thesecond amplifier stage, consisting of bipolar transistor Q11and its cascade-connected load resistance provided byPMOS transistors Q3 and Q5. The source of bias potentialsfor these PMOS transistors is subsequently described. MillerEffect compensation (roll-off) is accomplished by simplyconnecting a small capacitor between Terminals 1 and 8. A47pF capacitor provides sufficient compensation for stableunity-gain operation in most applications.

Bias-Source CircuitAt total supply voltages, somewhat above 8.3V, resistor R2and zener diode Z1 serve to establish a voltage of 8.3V acrossthe series-connected circuit, consisting of resistor R1, diodesD1 through D4, and PMOS transistor Q1. A tap at the junctionof resistor R1 and diode D4 provides a gate-bias potential ofabout 4.5V for PMOS transistors Q4 and Q5 with respect toTerminal 7. A potential of about 2.2V is developed acrossdiode-connected PMOS transistor Q1 with respect to Terminal7 to provide gate bias for PMOS transistors Q2 and Q3. Itshould be noted that Q1 is “mirror-connected (see Note 8)” toboth Q2 and Q3. Since transistors Q1, Q2, Q3 are designed tobe identical, the approximately 200µA current in Q1establishes a similar current in Q2 and Q3 as constant currentsources for both the first and second amplifier stages,respectively.

At total supply voltages somewhat less than 8.3V, zenerdiode Z1 becomes nonconductive and the potential,developed across series-connected R1, D1-D4, and Q1,varies directly with variations in supply voltage.Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies inaccordance with supply-voltage variations. This variationresults in deterioration of the power-supply-rejection ratio(PSRR) at total supply voltages below 8.3V. Operation attotal supply voltages below about 4.5V results in seriouslydegraded performance.

Output StageThe output stage consists of a drain-loaded invertingamplifier using CMOS transistors operating in the Class Amode. When operating into very high resistance loads, theoutput can be swung within millivolts of either supply rail.Because the output stage is a drain-loaded amplifier, its gainis dependent upon the load impedance. The transfercharacteristics of the output stage for a load returned to thenegative supply rail are shown in Figure 2. Typical op amploads are readily driven by the output stage. Because large-signal excursions are non-linear, requiring feedback for goodwaveform reproduction, transient delays may beencountered. As a voltage follower, the amplifier can achieve0.01% accuracy levels, including the negative supply rail.

NOTE:

8. For general information on the characteristics of CMOS transis-tor-pairs in linear-circuit applications, see File Number 619, datasheet on CA3600E “CMOS Transistor Array”.

Input Current Variation with Common Mode InputVoltageAs shown in the Table of Electrical Specifications, the inputcurrent for the CA3130 Series Op Amps is typically 5pA atTA = 25oC when Terminals 2 and 3 are at a common-modepotential of +7.5V with respect to negative supply Terminal 4.Figure 3 contains data showing the variation of input currentas a function of common-mode input voltage at TA = 25oC.

3

2

7

4

815

6

BIAS CKT.

COMPENSATION(WHEN REQUIRED)

AV ≈ 5XAV ≈ AV ≈

6000X 30XINPUT

+

-

200µA 200µA1.35mA 8mA

0mA

V+

OUTPUT

V-

STROBECC

OFFSETNULL

CA3130

(NOTE 7)

(NOTE 5)

NOTES:

6. Total supply voltage (for indicated voltage gains) = 15V with inputterminals biased so that Terminal 6 potential is +7.5V above Ter-minal 4.

7. Total supply voltage (for indicated voltage gains) = 15V with out-put terminal driven to either supply rail.

FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES

22.5

GATE VOLTAGE (TERMINALS 4 AND 8) (V)

OU

TP

UT

VO

LTA

GE

(T

ER

MIN

AL

S 4

AN

D 8

) (V

)

17.5 2012.5 15107.52.5 50

2.5

7.5

5

10

15

12.5

17.5

0

SUPPLY VOLTAGE: V+ = 15, V- = 0VTA = 25oC

LOAD RESISTANCE = 5kΩ

500Ω

1kΩ2kΩ

FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OFCMOS OUTPUT STAGE

CA3130, CA3130A

6

These data show that circuit designers can advantageouslyexploit these characteristics to design circuits which typicallyrequire an input current of less than 1pA, provided thecommon-mode input voltage does not exceed 2V. Aspreviously noted, the input current is essentially the result ofthe leakage current through the gate-protection diodes in theinput circuit and, therefore, a function of the applied voltage.Although the finite resistance of the glass terminal-to-caseinsulator of the metal can package also contributes anincrement of leakage current, there are useful compensatingfactors. Because the gate-protection network functions as if itis connected to Terminal 4 potential, and the Metal Can caseof the CA3130 is also internally tied to Terminal 4, inputTerminal 3 is essentially “guarded” from spurious leakagecurrents.

Offset NullingOffset-voltage nulling is usually accomplished with a100,000Ω potentiometer connected across Terminals 1 and5 and with the potentiometer slider arm connected toTerminal 4. A fine offset-null adjustment usually can beeffected with the slider arm positioned in the mid-point of thepotentiometer’s total range.

Input-Current Variation with TemperatureThe input current of the CA3130 Series circuits is typically5pA at 25oC. The major portion of this input current is due toleakage current through the gate-protective diodes in the inputcircuit. As with any semiconductor-junction device, includingop amps with a junction-FET input stage, the leakage currentapproximately doubles for every 10oC increase intemperature. Figure 4 provides data on the typical variation ofinput bias current as a function of temperature in the CA3130.

In applications requiring the lowest practical input currentand incremental increases in current because of “warm-up”effects, it is suggested that an appropriate heat sink be usedwith the CA3130. In addition, when “sinking” or “sourcing”significant output current the chip temperature increases,causing an increase in the input current. In such cases, heat-sinking can also very markedly reduce and stabilize inputcurrent variations.

Input Offset Voltage (VIO) Variation with DC Biasand Device Operating LifeIt is well known that the characteristics of a MOSFET devicecan change slightly when a DC gate-source bias potential isapplied to the device for extended time periods. Themagnitude of the change is increased at high temperatures.Users of the CA3130 should be alert to the possible impactsof this effect if the application of the device involvesextended operation at high temperatures with a significantdifferential DC bias voltage applied across Terminals 2 and3. Figure 5 shows typical data pertinent to shifts in offsetvoltage encountered with CA3130 devices (metal canpackage) during life testing. At lower temperatures (metalcan and plastic), for example at 85oC, this change in voltageis considerably less. In typical linear applications where thedifferential voltage is small and symmetrical, theseincremental changes are of about the same magnitude asthose encountered in an operational amplifier employing abipolar transistor input stage. The 2VDC differential voltageexample represents conditions when the amplifier outputstage is “toggled”, e.g., as in comparator applications.

10

7.5

5

2.5

0-1 0 1 2 3 4 5 6 7

INPUT CURRENT (pA)

INP

UT

VO

LTA

GE

(V

)

TA = 25oC

3

27

48

6PA

VIN

CA3130

15VTO5V

0VTO

-10V

V+

V-

FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE

VS = ±7.5V4000

1000

100

10

1-80 -60 -40 -20 0 20 40 60 80 100 120 140

INP

UT

CU

RR

EN

T (

pA

)

TEMPERATURE (oC)

FIGURE 4. INPUT CURRENT vs TEMPERATURE

CA3130, CA3130A

7

o

Power-Supply ConsiderationsBecause the CA3130 is very useful in single-supplyapplications, it is pertinent to review some considerationsrelating to power-supply current consumption under bothsingle-and dual-supply service. Figures 6A and 6B show theCA3130 connected for both dual-and single-supplyoperation.

Dual-supply Operation: When the output voltage at Terminal6 is 0V, the currents supplied by the two power supplies areequal. When the gate terminals of Q8 and Q12 are drivenincreasingly positive with respect to ground, current flow

through Q12 (from the negative supply) to the load isincreased and current flow through Q8 (from the positivesupply) decreases correspondingly. When the gate terminalsof Q8 and Q12 are driven increasingly negative with respectto ground, current flow through Q8 is increased and currentflow through Q12 is decreased accordingly.

Single-supply Operation: Initially, let it be assumed that thevalue of RL is very high (or disconnected), and that the input-terminal bias (Terminals 2 and 3) is such that the outputterminal (No. 6) voltage is at V+/2, i.e., the voltage dropsacross Q8 and Q12 are of equal magnitude. Figure 20 showstypical quiescent supply-current vs supply-voltage for theCA3130 operated under these conditions. Since the outputstage is operating as a Class A amplifier, the supply-currentwill remain constant under dynamic operating conditions aslong as the transistors are operated in the linear portion oftheir voltage-transfer characteristics (see Figure 2). If eitherQ8 or Q12 are swung out of their linear regions toward cut-off(a non-linear region), there will be a corresponding reductionin supply-current. In the extreme case, e.g., with Terminal 8swung down to ground potential (or tied to ground), NMOStransistor Q12 is completely cut off and the supply-current toseries-connected transistors Q8, Q12 goes essentially to zero.The two preceding stages in the CA3130, however, continueto draw modest supply-current (see the lower curve in Figure20) even though the output stage is strobed off. Figure 6Ashows a dual-supply arrangement for the output stage thatcan also be strobed off, assuming RL = ∞ by pulling thepotential of Terminal 8 down to that of Terminal 4.

Let it now be assumed that a load-resistance of nominalvalue (e.g., 2kΩ) is connected between Terminal 6 andground in the circuit of Figure 6B. Let it be assumed againthat the input-terminal bias (Terminals 2 and 3) is such thatthe output terminal (No. 6) voltage is at V+/2. Since PMOStransistor Q8 must now supply quiescent current to both RLand transistor Q12, it should be apparent that under theseconditions the supply-current must increase as an inversefunction of the RL magnitude. Figure 22 shows the voltage-drop across PMOS transistor Q8 as a function of loadcurrent at several supply voltages. Figure 2 shows thevoltage-transfer characteristics of the output stage forseveral values of load resistance.

Wideband NoiseFrom the standpoint of low-noise performanceconsiderations, the use of the CA3130 is mostadvantageous in applications where in the source resistanceof the input signal is on the order of 1MΩ or more. In thiscase, the total input-referred noise voltage is typically only23µV when the test-circuit amplifier of Figure 7 is operatedat a total supply voltage of 15V. This value of total input-referred noise remains essentially constant, even though thevalue of source resistance is raised by an order ofmagnitude. This characteristic is due to the fact thatreactance of the input capacitance becomes a significant

FIGURE 5. TYPICAL INCREMENTAL OFFSET-VOLTAGESHIFT vs OPERATING LIFE

FIGURE 6A. DUAL POWER SUPPLY OPERATION

FIGURE 6B. SINGLE POWER SUPPLY OPERATION

FIGURE 6. CA3130 OUTPUT STAGE IN DUAL AND SINGLEPOWER SUPPLY OPERATION

TA = 125oC FOR TO-5 PACKAGES7

6

5

4

3

2

1

0 500 1000 1500 2000 2500 3000 3500 4000

OF

FS

ET

VO

LTA

GE

SH

IFT

(m

V)

TIME (HOURS)

DIFFERENTIAL DC VOLTAGE(ACROSS TERMINALS 2 AND 3) = 0VOUTPUT VOLTAGE = V+ / 2

DIFFERENTIAL DC VOLTAGE(ACROSS TERMINALS 2 AND 3) = 2VOUTPUT STAGE TOGGLED

0

3

2

8

4

7

6

RL

Q8

Q12

CA3130+

-

V+

V-

3

2

8

4

7

6

RL

Q8

Q12

CA3130+

-

V+

CA3130, CA3130A

8

factor in shunting the source resistance. It should be noted,however, that for values of source resistance very muchgreater than 1MΩ, the total noise voltage generated can bedominated by the thermal noise contributions of both thefeedback and source resistors.

Typical Applications

Voltage FollowersOperational amplifiers with very high input resistances, likethe CA3130, are particularly suited to service as voltagefollowers. Figure 8 shows the circuit of a classical voltagefollower, together with pertinent waveforms using theCA3130 in a split-supply configuration.

A voltage follower, operated from a single supply, is shown inFigure 9, together with related waveforms. This followercircuit is linear over a wide dynamic range, as illustrated bythe reproduction of the output waveform in Figure 9A withinput-signal ramping. The waveforms in Figure 9B show thatthe follower does not lose its input-to-output phase-sense,even though the input is being swung 7.5V below groundpotential. This unique characteristic is an important attributein both operational amplifier and comparator applications.Figure 9B also shows the manner in which the CMOS outputstage permits the output signal to swing down to thenegative supply-rail potential (i.e., ground in the caseshown). The digital-to-analog converter (DAC) circuit,described later, illustrates the practical use of the CA3130 ina single-supply voltage-follower application.

9-Bit CMOS DACA typical circuit of a 9-bit Digital-to-Analog Converter (DAC)is shown in Figure 10. This system combines the concepts ofmultiple-switch CMOS lCs, a low-cost ladder network ofdiscrete metal-oxide-film resistors, a CA3130 op ampconnected as a follower, and an inexpensive monolithicregulator in a simple single power-supply arrangement. Anadditional feature of the DAC is that it is readily interfaced

with CMOS input logic, e.g., 10V logic levels are used in thecircuit of Figure 10.

The circuit uses an R/2R voltage-ladder network, with theoutput potential obtained directly by terminating the ladderarms at either the positive or the negative power-supplyterminal. Each CD4007A contains three “inverters”, each“inverter” functioning as a single-pole double-throw switch toterminate an arm of the R/2R network at either the positiveor negative power-supply terminal. The resistor ladder is anassembly of 1% tolerance metal-oxide film resistors. The fivearms requiring the highest accuracy are assembled withseries and parallel combinations of 806,000Ω resistors fromthe same manufacturing lot.

A single 15V supply provides a positive bus for the CA3130follower amplifier and feeds the CA3085 voltage regulator. A“scale-adjust” function is provided by the regulator outputcontrol, set to a nominal 10V level in this system. The line-voltage regulation (approximately 0.2%) permits a 9-bitaccuracy to be maintained with variations of several volts inthe supply. The flexibility afforded by the CMOS buildingblocks simplifies the design of DAC systems tailored toparticular needs.

Single-Supply, Absolute-Value, Ideal Full-WaveRectifierThe absolute-value circuit using the CA3130 is shown inFigure 11. During positive excursions, the input signal is fedthrough the feedback network directly to the output.Simultaneously, the positive excursion of the input signalalso drives the output terminal (No. 6) of the invertingamplifier in a negative-going excursion such that the 1N914diode effectively disconnects the amplifier from the signalpath. During a negative-going excursion of the input signal,the CA3130 functions as a normal inverting amplifier with again equal to -R2/R1. When the equality of the two equationsshown in Figure 11 is satisfied, the full-wave output issymmetrical.

Peak DetectorsPeak-detector circuits are easily implemented with theCA3130, as illustrated in Figure 12 for both the peak-positiveand the peak-negative circuit. It should be noted that withlarge-signal inputs, the bandwidth of the peak-negativecircuit is much less than that of the peak-positive circuit. Thesecond stage of the CA3130 limits the bandwidth in thiscase. Negative-going output-signal excursion requires apositive-going signal excursion at the collector of transistorQ11, which is loaded by the intrinsic capacitance of theassociated circuitry in this mode. On the other hand, duringa negative-going signal excursion at the collector of Q11, thetransistor functions in an active “pull-down” mode so that theintrinsic capacitance can be discharged more expeditiously.

3

2

18

4

7

6

+

-

Rs

1MΩ

47pF -7.5V

0.01µF

+7.5V

0.01µF

NOISEVOLTAGEOUTPUT

30.1kΩ

1kΩBW (-3dB) = 200kHzTOTAL NOISE VOLTAGE (REFERREDTO INPUT) = 23µV (TYP)

FIGURE 7. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USEDFOR WIDEBAND NOISE MEASUREMENTS

CA3130, CA3130A

9

3

2

18

4

7

6

+

-10kΩ

CC = 56pF-7.5V

0.01µF

+7.5V

0.01µF

2kΩ

2kΩ

BW (-3dB) = 4MHzSR = 10V/µs

25pF

0.1µF

Top Trace: Output

Center Trace: Input

FIGURE 8A. SMALL-SIGNAL RESPONSE (50mV/DIV.,200ns/DIV.)

Top Trace: Output Signal; 2V/Div., 5µs/Div.Center Trace: Difference Signa; 5mV/Div., 5µs/Div.

Bottom Trace: Input Signal; 2V/Div., 5µs/Div.

FIGURE 8B. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWINGSETTLING TIME (MEASUREMENT MADE WITHTEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER)

FIGURE 8. SPLIT SUPPLY VOLTAGE FOLLOWER WITHASSOCIATED WAVEFORMS

3

2

81

4

7

6

+

-

10kΩ

56pF OFFSET

+15V

0.01µF

2kΩ

0.1µF

5

ADJUST

100kΩ

FIGURE 9A. OUTPUT WAVEFORM WITH INPUT SIGNALRAMPING (2V/DIV., 500µs/DIV.)

Top Trace:Output; 5V/Div., 200µs/Div.Bottom Trace:Input Signal; 5V/Div., 200µs/Div.

FIGURE 9B. OUTPUT WAVEFORM WITH GROUNDREFERENCE SINE-WAVE INPUT

FIGURE 9. SINGLE SUPPLY VOLTAGE FOLLOWER WITHASSOCIATED WAVEFORMS. (e.g., FOR USE INSINGLE-SUPPLY D/A CONVERTER; SEE FIGURE 9IN AN6080)

CA3130, CA3130A

10

FIGURE 10. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130

FIGURE 11. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS

6 3 101036

4

8

36

7

9

4

10

2

3

13

812 12

1

58

1313 1 12

8 5

14

11

2

6

51

7

7

1

6

8

4

3

2

10V LOGIC INPUTS

+10.010V

LSB9 8 7 6 5 4 3 2 1

MSB

806K1%

PARALLELEDRESISTORS

+15V

VOLTAGEFOLLOWER

CA3130OUTPUT

LOAD

100KOFFSET

NULL

56pF

2K

0.1µF

REGULATEDVOLTAGE

ADJ

22.1k1%

1K

3.83k1%

0.001µF

CA3085

VOLTAGEREGULATOR+15V

2µF25V

+

-

+10.010V

CD4007A“SWITCHES”


402K1%

200K1%

100K1%

806K1%

806K1%

806K1%

750K1%

806K

1%806K1%

806K1%

806K1%

(2) (4) (8)

806K1%

+

-

62

BIT12345

6 - 9

REQUIREDRATIO-MATCH

STANDARD±0.1%±0.2%±0.4%±0.8%±1% ABS

NOTE: All resistances are in ohms.


1

5

10K

2

3 4

6

81

5

7

R2

2kΩ +15V

0.01µF

1N914

R3

5.1kΩ

PEAKADJUST

2kΩ100kΩ

OFFSETADJUST

20pF

CA3130

R1

4kΩ

+

-

20VP-P Input: BW(-3dB) = 230kHz, DC Output (Avg) = 3.2V1VP-P Input: BW(-3dB) = 130kHz, DC Output (Avg) = 160mV

ain =R2R1------- = X =

R3R1 + R2 + R3--------------------------------------

R3 = R1X + X

2

1 - X------------------

For X = 0.5:2KΩ4kΩ------------ =

R2R1-------

R3= 4kΩ 0.750.5

----------- = 6kΩ

Top Trace: Output Signal; 2V/Div.Bottom Trace: Input Signal; 10V/Div.Time base on both traces: 0.2ms/Div.

0V

0V

CA3130, CA3130A

11

FIGURE 12A. PEAK POSITIVE DETECTOR CIRCUIT FIGURE 12B. PEAK NEGATIVE DETECTOR CIRCUIT

FIGURE 12. PEAK-DETECTOR CIRCUITS

FIGURE 13. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)

3

26

4

7

CA3130

+7.5V

0.01µF

+DCOUTPUT

5µF+

-100kΩ

1N914

0.01µF

-7.5V2kΩ

10kΩ+

-

6VP-P INPUT;

BW (-3dB) = 1.3MHz

0.3VP-P INPUT;

BW (-3dB) = 240kHz3

26

4

7

CA3130

+7.5V

0.01µF

-DCOUTPUT

5µF+

-100kΩ

1N914

0.01µF

-7.5V2kΩ

10kΩ+

-

6VP-P INPUT;

BW (-3dB) = 360kHz

0.3VP-P INPUT;

BW (-3dB) = 320kHz

6

3

2

18

7

4

CA3086

CURRENTLIMITADJ

3Ω

R21kΩ

Q5 13

1412Q1Q2Q3Q4

10 7 3

426911 8 1 5

390Ω 1kΩ20kΩ

+

-5µF25V

56pF

ERRORAMPLIFIER

CA3130

30kΩ

100kΩ

IC1

0.01VOLTAGEADJUST

50kΩR1

14

13

Q5

12

62kΩ

IC3

OUTPUT0 TO 13V

AT40mA

+

-

0.01µF

+20VINPUT

2.2kΩ

+- 25µFIC2

CA3086 10 11 1, 2Q4 Q1

8, 7 5Q3 Q2

6 4

REGULATION (NO LOAD TO FULL LOAD): <0.01%INPUT REGULATION: 0.02%/VHUM AND NOISE OUTPUT: <25µV UP TO 100kHz

+

-

+

-

1kΩ

9

µF

3

CA3130, CA3130A

12

Error-Amplifier in Regulated-Power SuppliesThe CA3130 is an ideal choice for error-amplifier service inregulated power supplies since it can function as an error-amplifier when the regulated output voltage is required toapproach zero. Figure 13 shows the schematic diagram of a40mA power supply capable of providing regulated outputvoltage by continuous adjustment over the range from 0V to13V. Q3 and Q4 in lC2 (a CA3086 transistor-array lC)function as zeners to provide supply-voltage for the CA3130comparator (IC1). Q1, Q2, and Q5 in IC2 are configured as alow impedance, temperature-compensated source ofadjustable reference voltage for the error amplifier.Transistors Q1, Q2, Q3, and Q4 in lC3 (another CA3086transistor-array lC) are connected in parallel as the series-pass element. Transistor Q5 in lC3 functions as a current-limiting device by diverting base drive from the series-passtransistors, in accordance with the adjustment of resistor R2.

Figure 14 contains the schematic diagram of a regulatedpower-supply capable of providing regulated output voltageby continuous adjustment over the range from 0.1V to 50Vand currents up to 1A. The error amplifier (lC1) and circuitryassociated with lC2 function as previously described,although the output of lC1 is boosted by a discrete transistor(Q4) to provide adequate base drive for the Darlington-

connected series-pass transistors Q1, Q2. Transistor Q3functions in the previously described current-limiting circuit.

MultivibratorsThe exceptionally high input resistance presented by theCA3130 is an attractive feature for multivibrator circuitdesign because it permits the use of timing circuits with highR/C ratios. The circuit diagram of a pulse generator (astablemultivibrator), with provisions for independent control of the“on” and “off” periods, is shown in Figure 15. Resistors R1and R2 are used to bias the CA3130 to the mid-point of thesupply-voltage and R3 is the feedback resistor. The pulserepetition rate is selected by positioning S1 to the desiredposition and the rate remains essentially constant when theresistors which determine “on-period” and “off-period” areadjusted.

Function GeneratorFigure 16 contains a schematic diagram of a functiongenerator using the CA3130 in the integrator and thresholddetector functions. This circuit generates a triangular orsquare-wave output that can be swept over a 1,000,000:1range (0.1Hz to 100kHz) by means of a single control, R1. Avoltage-control input is also available for remote sweep-control.

FIGURE 14. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)

6

2

3

18

7

4

4.3kΩ

1Ω

+

-43kΩ 100µF

ERRORAMPLIFIER

IC1

VOLTAGEADJUST

14

13

100µF

+55VINPUT

2.2kΩ

+-IC2

CA3086 10, 11

Q4 Q1

Q2

6

REGULATION (NO LOAD TO FULL LOAD): <0.005%INPUT REGULATION: 0.01%/VHUM AND NOISE OUTPUT: <250µVRMS UP TO 100kHz

+

-

+

-

CA3130

+

-

+-

1W

3.3kΩ1W

5µF

98, 7

Q3

1, 2

35

4

1kΩ

62kΩ

Q5

12

10kΩ

Q2

Q1

50kΩ

Q3

1kΩ

2N3055

2N2102CURRENTLIMITADJUST

2N5294

2N2102

Q4

1000pF

10kΩ

8.2kΩ

OUTPUT:0.1 TO 50V

AT 1A

CA3130, CA3130A

13

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate andreliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may resultfrom its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

The heart of the frequency-determining system is anoperational-transconductance-amplifier (OTA) (see Note 10),lC1, operated as a voltage-controlled current-source. Theoutput, IO, is a current applied directly to the integratingcapacitor, C1, in the feedback loop of the integrator lC2, usinga CA3130, to provide the triangular-wave output.Potentiometer R2 is used to adjust the circuit for slopesymmetry of positive-going and negative-going signalexcursions.

Another CA3130, IC3, is used as a controlled switch to setthe excursion limits of the triangular output from theintegrator circuit. Capacitor C2 is a “peaking adjustment” tooptimize the high-frequency square-wave performance ofthe circuit.

Potentiometer R3 is adjustable to perfect the “amplitudesymmetry” of the square-wave output signals. Output fromthe threshold detector is fed back via resistor R4 to the inputof lC1 so as to toggle the current source from plus to minusin generating the linear triangular wave.

Operation with Output-Stage Power-BoosterThe current-sourcing and-sinking capability of the CA3130output stage is easily supplemented to provide power-boostcapability. In the circuit of Figure 17, three CMOS transistor-pairs in a single CA3600E (see Note 12) lC array are shownparallel connected with the output stage in the CA3130. Inthe Class A mode of CA3600E shown, a typical deviceconsumes 20mA of supply current at 15V operation. Thisarrangement boosts the current-handling capability of theCA3130 output stage by about 2.5X.

The amplifier circuit in Figure 17 employs feedback toestablish a closed-loop gain of 48dB. The typical large-signalbandwidth (-3dB) is 50kHz.

NOTE:

9. See file number 619 for technical information.

7

4

6

3

2

R1100kΩ

R2100kΩ

R3100kΩ

ON-PERIODADJUST

1MΩ

2kΩ 2kΩ

OFF-PERIODADJUST

1MΩ

+15V

0.01µF

OUTPUT

2kΩ

0.001µF0.01µF

0.1µF

1µF S1CA3130

+

-

FIGURE 15. PULSE GENERATOR (ASTABLE MULTIVIBRATOR)WITH PROVISIONS FOR INDEPENDENT CONTROLOF “ON” AND “OFF” PERIODS

FREQUENCY RANGE:

POSITION OF S10.001µF

0.01µF0.1µF

1µF

PULSE PERIOD4µs to 1ms40µs to 10ms0.4ms to 100ms4ms to 1s

CA3130, CA3130A

14

NOTE:

10. See file number 475 and AN6668 for technical information.

FIGURE 16. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)

NOTES:

11. Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the CA3130.

12. See file number 619.

FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3130

6

3

2

1

4

7

5

6

2

34

7

8

1

5

4

6

7

3

2

R4

270kΩ

+7.5V

VOLTAGE-CONTROLLEDCURRENT SOURCE

IC1

3kΩ3kΩ

10MΩ+7.5V

R2100kΩ SLOPE

SYMMETRYADJUST

VOLTAGECONTROLLEDINPUT

-7.5V

10kΩ

10kΩR1

-7.5V

FREQUENCYADJUST(100kHz MAX)

-7.5V

+7.5V

IOIC2

+7.5V

C1

100pF

INTEGRATOR

-7.5V

56pF

CA3130+

-

CA3080A

+

-39kΩ

3 - 30pF

C2

ADJUSTHIGH - FREQ. DETECTOR

THRESHOLD

150kΩ

IC3

+7.5V

CA3130

+

-

R3100kΩ

AMPLITUDESYMMETRYADJUST

22kΩ

-7.5V

(NOTE 10)

8

7

3

2

+15V

2kΩ CA3130

+

-

41036

4 97

6

14

750kΩ

1µF

2 11

13 1

12

58

1µF

1MΩ0.01µF

510kΩ

500µF

QP3

QN1 QN2 QN3

QP2QP1

CA3600E

AV(CL) = 48dB

LARGE SIGNALBW (-3 dB) = 50kHz

RL = 100Ω(PO = 150mW

AT THD = 10%)

(NOTE 12)

INPUT

CA3130, CA3130A

15

Typical Performance Curves

FIGURE 18. OPEN LOOP GAIN vs TEMPERATURE FIGURE 19. OPEN-LOOP RESPONSE

FIGURE 20. QUIESCENT SUPPLY CURRENT vs SUPPLYVOLTAGE

FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLYVOLTAGE

FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR(Q8) vs LOAD CURRENT

FIGURE 23. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR(Q12) vs LOAD CURRENT

LOAD RESISTANCE = 2kΩ150

140

130

120

110

100

90

80-100 -50 0 50 100

OP

EN

LO

OP

VO

LTA

GE

GA

IN (

dB

)

TEMPERATURE (oC)

SUPPLY VOLTAGE: V+ = 15V; V- = 0TA = 25oC

φ OL

3

2

1

1

2

3

4

4

AOL

1 - CL = 9pF, CC = 0pF, RL = ∞2 - CL = 30pF, CC = 15pF, RL = 2kΩ3 - CL = 30pF, CC = 47pF, RL = 2kΩ4 - CL = 30pF, CC = 150pF, RL = 2kΩ

120

100

80

60

40

20

0

OP

EN

LO

OP

VO

LTA

GE

GA

IN (

dB

)

-100

-200

-300

OP

EN

LO

OP

PH

AS

E (

DE

GR

EE

S)

102 103 104 105 106 107 108

FREQUENCY (Hz)101

LOAD RESISTANCE = ∞TA = 25oCV- = 0 OUTPUT VOLTAGE BALANCED = V+/2

OUTPUT VOLTAGE HIGH = V+OR LOW = V-

17.5

12.5

10

7.5

5

2.5

06 8 10 12 14 16 18

TOTAL SUPPLY VOLTAGE (V)

QU

IES

CE

NT

SU

PP

LY C

UR

RE

NT

(m

A)

4

OUTPUT VOLTAGE = V+/2V- = 0

14

12

10

8

6

4

2

0 2 4 6 8 10 12 14 16

QU

IES

CE

NT

SU

PP

LY C

UR

RE

NT

(m

A)

TOTAL SUPPLY VOLTAGE (V)

TA = -55oC

25oC

125oC

0

50

10

1

0.1

0.01

0.0010.001 0.01 0.1 1.0 10 100

MAGNITUDE OF LOAD CURRENT (mA)

VO

LTA

GE

DR

OP

AC

RO

SS

PM

OS

OU

TP

UT

STA

GE

TR

AN

SIS

TOR

(V

)

15V10V

NEGATIVE SUPPLY VOLTAGE = 0VTA = 25oC

POSITIVE SUPPLY VOLTAGE = 5V

NEGATIVE SUPPLY VOLTAGE = 0VTA = 25oC

50

10

1

0.1

0.01

0.0010.001 0.01 0.1 1 10 100

MAGNITUDE OF LOAD CURRENT (mA)

VO

LTA

GE

DR

OP

AC

RO

SS

NM

OS

OU

TP

UT

STA

GE

TR

AN

SIS

TOR

(V

)

15V10V

POSITIVE SUPPLY VOLTAGE = 5V

CA3130, CA3130A

1

TM

tle80

-

ci-

e-

er-/Voe-edil-r)tho

-dsr-

po-n,i-

or,e-

ra-

-

edlla-

i-,

NOT RECOM

ICL8038MENDED FOR NEW DESIGNS

File Number 2864.4Data Sheet April 2001

Precision Waveform Generator/VoltageControlled OscillatorThe ICL8038 waveform generator is a monolithic integratedcircuit capable of producing high accuracy sine, square,triangular, sawtooth and pulse waveforms with a minimum ofexternal components. The frequency (or repetition rate) canbe selected externally from 0.001Hz to more than 300kHzusing either resistors or capacitors, and frequencymodulation and sweeping can be accomplished with anexternal voltage. The ICL8038 is fabricated with advancedmonolithic technology, using Schottky barrier diodes and thinfilm resistors, and the output is stable over a wide range oftemperature and supply variations. These devices may beinterfaced with phase locked loop circuitry to reducetemperature drift to less than 250ppm/oC.

Features

• Low Frequency Drift with Temperature. . . . . . 250ppm/oC

• Low Distortion . . . . . . . . . . . . . . . 1% (Sine Wave Output)

• High Linearity . . . . . . . . . . . 0.1% (Triangle Wave Output)

• Wide Frequency Range . . . . . . . . . . . .0.001Hz to 300kHz

• Variable Duty Cycle . . . . . . . . . . . . . . . . . . . . . 2% to 98%

• High Level Outputs. . . . . . . . . . . . . . . . . . . . . . TTL to 28V

• Simultaneous Sine, Square, and Triangle WaveOutputs

• Easy to Use - Just a Handful of External ComponentsRequired

PinoutICL8038

(PDIP, CERDIP)TOP VIEW

Functional Diagram

Ordering Information

PART NUMBER STABILITY TEMP. RANGE (oC) PACKAGE PKG. NO.

ICL8038CCPD 250ppm/oC (Typ) 0 to 70 14 Ld PDIP E14.3

ICL8038CCJD 250ppm/oC (Typ) 0 to 70 14 Ld CERDIP F14.3

ICL8038BCJD 180ppm/oC (Typ) 0 to 70 14 Ld CERDIP F14.3

ICL8038ACJD 120ppm/oC (Typ) 0 to 70 14 Ld CERDIP F14.3

SINE

TRIANGLE

DUTY CYCLE

V+

FM BIAS

NC

NC

SINE WAVE

V- OR GND

TIMING

SQUARE

FM SWEEP

1

2

3

4

5

6

7

14

13

12

11

10

9

8

ADJUST

CAPACITOR

WAVE OUT

INPUT

SINE WAVEADJUST

WAVE OUT

OUT

FREQUENCYADJUST

COMPARATOR#1

COMPARATOR#2

FLIP-FLOP

SINECONVERTERBUFFERBUFFER

9 2

11

I10

6V+

V- OR GND

CURRENTSOURCE

#1

CURRENTSOURCE

#2

2IC

3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 2001, All Rights Reserved

ICL8038

Absolute Maximum Ratings Thermal Information

Supply Voltage (V- to V+). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36VInput Voltage (Any Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to V+Input Current (Pins 4 and 5). . . . . . . . . . . . . . . . . . . . . . . . . . . 25mAOutput Sink Current (Pins 3 and 9) . . . . . . . . . . . . . . . . . . . . . 25mA

Operating ConditionsTemperature Range

ICL8038AC, ICL8038BC, ICL8038CC . . . . . . . . . . . . 0oC to 70oC

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)CERDIP Package. . . . . . . . . . . . . . . . . 75 20PDIP Package . . . . . . . . . . . . . . . . . . . 115 N/A

Maximum Junction Temperature (Ceramic Package) . . . . . . . .175oCMaximum Junction Temperature (Plastic Package) . . . . . . . .150oCMaximum Storage Temperature Range. . . . . . . . . . -65oC to 150oCMaximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

Die CharacteristicsBack Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications VSUPPLY = ±10V or +20V, TA = 25oC, RL = 10kΩ, Test Circuit Unless Otherwise Specified


CONDITIONS

ICL8038CC ICL8038BC ICL8038AC

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Supply Voltage Operating Range VSUPPLY

V+ Single Supply +10 - +30 +10 - +30 +10 - +30 V

V+, V- Dual Supplies ±5 - ±15 ±5 - ±15 ±5 - ±15 V

Supply Current ISUPPLY VSUPPLY = ±10V(Note 2)

12 20 - 12 20 - 12 20 mA

FREQUENCY CHARACTERISTICS (All Waveforms)

Max. Frequency of Oscillation fMAX 100 - - 100 - - 100 - - kHz

Sweep Frequency of FM Input fSWEEP - 10 - - 10 - - 10 - kHz

Sweep FM Range (Note 3) - 35:1 - - 35:1 - - 35:1 -

FM Linearity 10:1 Ratio - 0.5 - - 0.2 - - 0.2 - %

Frequency Drift withTemperature (Note 5)

∆f/∆T 0oC to 70oC - 250 - - 180 - - 120 ppm/oC

Frequency Drift with Supply Voltage ∆f/∆V Over SupplyVoltage Range

- 0.05 - - 0.05 - 0.05 - %/V

OUTPUT CHARACTERISTICS

Square Wave

Leakage Current IOLK V9 = 30V - - 1 - - 1 - - 1 µA

Saturation Voltage VSAT ISINK = 2mA - 0.2 0.5 - 0.2 0.4 - 0.2 0.4 V

Rise Time tR RL = 4.7kΩ - 180 - - 180 - - 180 - ns

Fall Time tF RL = 4.7kΩ - 40 - - 40 - - 40 - ns

Typical Duty Cycle Adjust(Note 6)

∆D 2 98 2 - 98 2 - 98 %

Triangle/Sawtooth/Ramp -

Amplitude VTRIAN-GLE

RTRI = 100kΩ 0.30 0.33 - 0.30 0.33 - 0.30 0.33 - xVSUPPLY

Linearity - 0.1 - - 0.05 - - 0.05 - %

Output Impedance ZOUT IOUT = 5mA - 200 - - 200 - - 200 - Ω

2

ICL8038

Sine Wave

Amplitude VSINE RSINE = 100kΩ 0.2 0.22 - 0.2 0.22 - 0.2 0.22 - xVSUPPLY

THD THD RS = 1MΩ(Note 4)

- 2.0 5 - 1.5 3 - 1.0 1.5 %

THD Adjusted THD Use Figure 4 - 1.5 - - 1.0 - - 0.8 - %

NOTES:

2. RA and RB currents not included.

3. VSUPPLY = 20V; RA and RB = 10kΩ, f ≅ 10kHz nominal; can be extended 1000 to 1. See Figures 5A and 5B.

4. 82kΩ connected between pins 11 and 12, Triangle Duty Cycle set at 50%. (Use RA and RB.)

5. Figure 1, pins 7 and 8 connected, VSUPPLY = ±10V. See Typical Curves for T.C. vs VSUPPLY.

6. Not tested, typical value for design purposes only.

Electrical Specifications VSUPPLY = ±10V or +20V, TA = 25oC, RL = 10kΩ, Test Circuit Unless Otherwise Specified (Continued)


CONDITIONS

ICL8038CC ICL8038BC ICL8038AC

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Test Conditions

PARAMETER RA RB RL C SW1 MEASURE

Supply Current 10kΩ 10kΩ 10kΩ 3.3nF Closed Current Into Pin 6

Sweep FM Range (Note 7) 10kΩ 10kΩ 10kΩ 3.3nF Open Frequency at Pin 9

Frequency Drift with Temperature 10kΩ 10kΩ 10kΩ 3.3nF Closed Frequency at Pin 3

Frequency Drift with Supply Voltage (Note 8) 10kΩ 10kΩ 10kΩ 3.3nF Closed Frequency at Pin 9

Output Amplitude (Note 10)

Sine 10kΩ 10kΩ 10kΩ 3.3nF Closed Pk-Pk Output at Pin 2

Triangle 10kΩ 10kΩ 10kΩ 3.3nF Closed Pk-Pk Output at Pin 3

Leakage Current (Off) (Note 9) 10kΩ 10kΩ 3.3nF Closed Current into Pin 9

Saturation Voltage (On) (Note 9) 10kΩ 10kΩ 3.3nF Closed Output (Low) at Pin 9

Rise and Fall Times (Note 11) 10kΩ 10kΩ 4.7kΩ 3.3nF Closed Waveform at Pin 9

Duty Cycle Adjust (Note 11)

Max 50kΩ ~1.6kΩ 10kΩ 3.3nF Closed Waveform at Pin 9

Min ~25kΩ 50kΩ 10kΩ 3.3nF Closed Waveform at Pin 9

Triangle Waveform Linearity 10kΩ 10kΩ 10kΩ 3.3nF Closed Waveform at Pin 3

Total Harmonic Distortion 10kΩ 10kΩ 10kΩ 3.3nF Closed Waveform at Pin 2

NOTES:7. The hi and lo frequencies can be obtained by connecting pin 8 to pin 7 (fHI) and then connecting pin 8 to pin 6 (fLO). Otherwise apply Sweep

Voltage at pin 8 (2/3 VSUPPLY +2V) ≤ VSWEEP ≤ VSUPPLY where VSUPPLY is the total supply voltage. In Figure 5B, pin 8 should vary between5.3V and 10V with respect to ground.

8. 10V ≤ V+ ≤ 30V, or ±5V ≤ VSUPPLY ≤ ±15V.9. Oscillation can be halted by forcing pin 10 to +5V or -5V.

10. Output Amplitude is tested under static conditions by forcing pin 10 to 5V then to -5V.11. Not tested; for design purposes only.

3

ICL8038

Test Circuit

Application Information (See Functional Diagram)

An external capacitor C is charged and discharged by twocurrent sources. Current source #2 is switched on and off by aflip-flop, while current source #1 is on continuously. Assumingthat the flip-flop is in a state such that current source #2 is off,and the capacitor is charged with a current I, the voltageacross the capacitor rises linearly with time. When this voltagereaches the level of comparator #1 (set at 2/3 of the supplyvoltage), the flip-flop is triggered, changes states, andreleases current source #2. This current source normallycarries a current 2I, thus the capacitor is discharged with a

net-current I and the voltage across it drops linearly with time.When it has reached the level of comparator #2 (set at 1/3 ofthe supply voltage), the flip-flop is triggered into its originalstate and the cycle starts again.

Four waveforms are readily obtainable from this basicgenerator circuit. With the current sources set at I and 2Irespectively, the charge and discharge times are equal.Thus a triangle waveform is created across the capacitorand the flip-flop produces a square wave. Both waveformsare fed to buffer stages and are available at pins 3 and 9.

Detailed Schematic

ICL8038

4 5 6 9

2121110

8

7

SW1N.C.

C3300pF

82K

RA10K

RB10K

RL10K

RTRI

RSINE

-10V

3

+10V

FIGURE 1. TEST CIRCUIT

Q20Q21

Q19Q22Q31

Q32

Q33

Q34

Q30

Q7

Q6

Q1Q2

Q4

Q8 Q9

Q5

Q3

Q14

Q11Q12

Q13

Q24

Q23

Q25

Q26

Q29

Q27Q28

Q10

Q15Q18

Q17Q16

Q35

Q36 Q38 Q40

Q37 Q39

R111K

R239K

7

8 5 4

REXT B REXT A

COMPARATOR

R414K

R85K

R95K

R105K

R4327K

R4227K

BUFFER AMPLIFIER

R4127K

R174.7K

R184.7K

R1427K

R13620

R161.8K

R6100

R5100

R4100

R330K

R4640K CEXT

R7A

10K

R7B

15K

R441K

3

10

R11270

R122.7K

R15470

R24

800

2

R21

10K

R20

2.7K

R19

800

FLIP-FLOPSINE CONVERTER

Q49

Q50

Q52

Q51

Q53

Q55

Q54

Q56

Q42

Q41

Q43

Q44

Q45

Q46

Q47

Q48

6V+

1

12

R325.2K

R33200

R34375

R35330

R361600

R37330

R38375

R39200

R405.6K

REXTC82K

R23

2.7K

R22

10K

R2833K

R3033K

R2933K

R3133K

R2533K

R2633K

R2733K

R4533K

CURRENT SOURCES

9

11

4

ICL8038

The levels of the current sources can, however, be selectedover a wide range with two external resistors. Therefore, withthe two currents set at values different from I and 2I, anasymmetrical sawtooth appears at Terminal 3 and pulseswith a duty cycle from less than 1% to greater than 99% areavailable at Terminal 9.

The sine wave is created by feeding the triangle wave into anonlinear network (sine converter). This network provides adecreasing shunt impedance as the potential of the trianglemoves toward the two extremes.

Waveform TimingThe symmetry of all waveforms can be adjusted with theexternal timing resistors. Two possible ways to accomplishthis are shown in Figure 3. Best results are obtained bykeeping the timing resistors RA and RB separate (A). RAcontrols the rising portion of the triangle and sine wave andthe 1 state of the square wave.

The magnitude of the triangle waveform is set at 1/3VSUPPLY; therefore the rising portion of the triangle is,

The falling portion of the triangle and sine wave and the 0state of the square wave is:

Thus a 50% duty cycle is achieved when RA = RB.

If the duty cycle is to be varied over a small range about 50%only, the connection shown in Figure 3B is slightly moreconvenient. A 1kΩ potentiometer may not allow the duty cycleto be adjusted through 50% on all devices. If a 50% duty cycleis required, a 2kΩ or 5kΩ potentiometer should be used.

With two separate timing resistors, the frequency is given by:

or, if RA = RB = R

t1C V×

I--------------

C 1/3 VSUPPLY RA×××0.22 VSUPPLY×

-------------------------------------------------------------------RA C×

0.66------------------= = =

t2C V×

1-------------

C 1/3VSUPPLY×

2 0.22( )VSUPPLY

RB------------------------ 0.22

VSUPPLYRA

------------------------–

-----------------------------------------------------------------------------------RARBC

0.66 2RA RB–( )-------------------------------------= = =

f 1t1 t2+----------------

1

RAC

0.66------------ 1

RB2RA RB–-------------------------+

------------------------------------------------------= =

f 0.33RC----------- (for Figure 3A)=

FIGURE 2A. SQUARE WAVE DUTY CYCLE - 50% FIGURE 2B. SQUARE WAVE DUTY CYCLE - 80%

FIGURE 2. PHASE RELATIONSHIP OF WAVEFORMS

FIGURE 3A. FIGURE 3B.

FIGURE 3. POSSIBLE CONNECTIONS FOR THE EXTERNAL TIMING RESISTORS

C 82K

ICL8038

4 5 6 9

2121110

8

7

RA RL

V- OR GND

3

RB

V+

ICL8038

4 5 6 9

2121110

8

7

C 100K

RARL

V- OR GND

3

RB

V+

1kΩ

5

ICL8038

Neither time nor frequency are dependent on supply voltage,even though none of the voltages are regulated inside theintegrated circuit. This is due to the fact that both currentsand thresholds are direct, linear functions of the supplyvoltage and thus their effects cancel.

Reducing DistortionTo minimize sine wave distortion the 82kΩ resistor betweenpins 11 and 12 is best made variable. With this arrangementdistortion of less than 1% is achievable. To reduce this evenfurther, two potentiometers can be connected as shown inFigure 4; this configuration allows a typical reduction of sinewave distortion close to 0.5%.

Selecting RA, RB and CFor any given output frequency, there is a wide range of RCcombinations that will work, however certain constraints areplaced upon the magnitude of the charging current foroptimum performance. At the low end, currents of less than1µA are undesirable because circuit leakages will contributesignificant errors at high temperatures. At higher currents(I > 5mA), transistor betas and saturation voltages willcontribute increasingly larger errors. Optimum performancewill, therefore, be obtained with charging currents of 10µA to1mA. If pins 7 and 8 are shorted together, the magnitude ofthe charging current due to RA can be calculated from:

R1 and R2 are shown in the Detailed Schematic.

A similar calculation holds for RB.

The capacitor value should be chosen at the upper end of itspossible range.

Waveform Out Level Control and Power SuppliesThe waveform generator can be operated either from asingle power supply (10V to 30V) or a dual power supply(±5V to ±15V). With a single power supply the averagelevels of the triangle and sine wave are at exactly one-half ofthe supply voltage, while the square wave alternatesbetween V+ and ground. A split power supply has theadvantage that all waveforms move symmetrically aboutground.

The square wave output is not committed. A load resistorcan be connected to a different power supply, as long as theapplied voltage remains within the breakdown capability ofthe waveform generator (30V). In this way, the square waveoutput can be made TTL compatible (load resistorconnected to +5V) while the waveform generator itself ispowered from a much higher voltage.

Frequency Modulation and SweepingThe frequency of the waveform generator is a direct functionof the DC voltage at Terminal 8 (measured from V+). Byaltering this voltage, frequency modulation is performed. Forsmall deviations (e.g. ±10%) the modulating signal can beapplied directly to pin 8, merely providing DC decouplingwith a capacitor as shown in Figure 5A. An external resistorbetween pins 7 and 8 is not necessary, but it can be used toincrease input impedance from about 8kΩ (pins 7 and 8connected together), to about (R + 8kΩ).

For larger FM deviations or for frequency sweeping, themodulating signal is applied between the positive supplyvoltage and pin 8 (Figure 5B). In this way the entire bias forthe current sources is created by the modulating signal, anda very large (e.g. 1000:1) sweep range is created(f = Minimum at VSWEEP = 0, i.e., Pin 8 = V+). Care must betaken, however, to regulate the supply voltage; in thisconfiguration the charge current is no longer a function of thesupply voltage (yet the trigger thresholds still are) and thusthe frequency becomes dependent on the supply voltage.The potential on Pin 8 may be swept down from V+ by (1/3VSUPPLY - 2V).

ICL8038

4 5 6 9

2121110

8

7

C100kΩ

RARL

V- OR GND

3

RB

V+

1kΩ

110kΩ100kΩ

10kΩ

FIGURE 4. CONNECTION TO ACHIEVE MINIMUM SINE WAVEDISTORTION

IR1 V+ V-–( )×

R1 R2+( )----------------------------------------

1RA--------× 0.22 V+ V-–( )

RA------------------------------------= =

C 81K

ICL8038

4 5 6 9

2121110

8

7

RA RL

V- OR GND

3

RB

V+

R

FM

FIGURE 5A. CONNECTIONS FOR FREQUENCY MODULATION

6

ICL8038

Typical ApplicationsThe sine wave output has a relatively high output impedance(1kΩ Typ). The circuit of Figure 6 provides buffering, gainand amplitude adjustment. A simple op amp follower couldalso be used.

With a dual supply voltage the external capacitor on Pin 10 canbe shorted to ground to halt the ICL8038 oscillation. Figure 7shows a FET switch, diode ANDed with an input strobe signalto allow the output to always start on the same slope.

To obtain a 1000:1 Sweep Range on the ICL8038 thevoltage across external resistors RA and RB must decreaseto nearly zero. This requires that the highest voltage oncontrol Pin 8 exceed the voltage at the top of RA and RB by afew hundred mV. The Circuit of Figure 8 achieves this byusing a diode to lower the effective supply voltage on theICL8038. The large resistor on pin 5 helps reduce duty cyclevariations with sweep.

The linearity of input sweep voltage versus output frequencycan be significantly improved by using an op amp as shownin Figure 10.

C 81K

ICL8038

4 5 6 9

2121110

8

RA RL

V- OR GND

3

RB

V+

SWEEPVOLTAGE

FIGURE 5B. CONNECTIONS FOR FREQUENCY SWEEPFIGURE 5.

C

ICL8038

4 5 6 2

1110

8

7

RA

100K

V-

RB

V+

AMPLITUDE

20K

+

-741

4.7K

FIGURE 6. SINE WAVE OUTPUT BUFFER AMPLIFIERS

C

ICL8038

4 5 9

1011

8

7

RA

1N914

-15V

RB

V+

STROBE

2

2N4392

1N914

15K

100K

OFF

ON

+15V (+10V)-15V (-10V)

FIGURE 7. STROBE TONE BURST GENERATOR

0.0047µF DISTORTION

ICL8038

5 4 6 9

2121110

8

4.7K

-10V

3

+10V

20K

4.7K1K

DUTY CYCLE

15K

1N457

0.1µF

100K≈15M

10KFREQ.

FIGURE 8. VARIABLE AUDIO OSCILLATOR, 20Hz TO 20kHzY

7

ICL8038

Use in Phase Locked LoopsIts high frequency stability makes the ICL8038 an idealbuilding block for a phase locked loop as shown in Figure 9.In this application the remaining functional blocks, the phasedetector and the amplifier, can be formed by a number ofavailable ICs (e.g., MC4344, NE562).

In order to match these building blocks to each other, twosteps must be taken. First, two different supply voltages areused and the square wave output is returned to the supply ofthe phase detector. This assures that the VCO input voltagewill not exceed the capabilities of the phase detector. If asmaller VCO signal is required, a simple resistive voltagedivider is connected between pin 9 of the waveformgenerator and the VCO input of the phase detector.

Second, the DC output level of the amplifier must be madecompatible to the DC level required at the FM input of thewaveform generator (pin 8, 0.8V+). The simplest solution hereis to provide a voltage divider to V+ (R1, R2 as shown) if theamplifier has a lower output level, or to ground if its level ishigher. The divider can be made part of the low-pass filter.

This application not only provides for a free-runningfrequency with very low temperature drift, but is also has theunique feature of producing a large reconstituted sinewavesignal with a frequency identical to that at the input.

For further information, see Intersil Application Note AN013,“Everything You Always Wanted to Know About the ICL8038”.

SINE WAVE

ICL8038

4 5 6 3

11211108

7

R1

V-/GND

2

DUTYV2+

CYCLEFREQUENCY

ADJUST

ADJ.

9

SINE WAVE

TRIANGLEOUT

SINE WAVEADJ.

TIMINGCAP.

FM BIAS

SQUAREWAVE

OUT

R2

LOW PASSFILTER

DEMODULATEDFMAMPLIFIERPHASE

DETECTOR

VCOININPUT

V1+

OUT

FIGURE 9. WAVEFORM GENERATOR USED AS STABLE VCO IN A PHASE-LOCKED LOOP

3,900pF SINE WAVE

ICL8038

4 5 6 9

2121110

8

4.7kΩ

3

4.7kΩ500Ω 10kΩ

1N753A

DISTORTION

FUNCTION GENERATOR

100kΩ

+

50µF15V

1MΩ(6.2V)

HIGH FREQUENCYSYMMETRY

100kΩ

LOW FREQUENCYSYMMETRY

100kΩ

+

-741

+15V

-15V

SINE WAVEOUTPUT

+

-741

+15V

1kΩ

10kΩOFFSET

-VIN P4

1,000pF

1kΩ

FIGURE 10. LINEAR VOLTAGE CONTROLLED OSCILLATOR

8

ICL8038

Definition of TermsSupply Voltage (VSUPPLY). The total supply voltage fromV+ to V-.

Supply Current. The supply current required from thepower supply to operate the device, excluding load currentsand the currents through RA and RB.

Frequency Range. The frequency range at the square waveoutput through which circuit operation is guaranteed.

Sweep FM Range. The ratio of maximum frequency tominimum frequency which can be obtained by applying asweep voltage to pin 8. For correct operation, the sweepvoltage should be within the range:

(2/3 VSUPPLY + 2V) < VSWEEP < VSUPPLY

FM Linearity. The percentage deviation from the best fitstraight line on the control voltage versus output frequencycurve.

Output Amplitude. The peak-to-peak signal amplitudeappearing at the outputs.

Saturation Voltage. The output voltage at the collector ofQ23 when this transistor is turned on. It is measured for asink current of 2mA.

Rise and Fall Times. The time required for the square waveoutput to change from 10% to 90%, or 90% to 10%, of itsfinal value.

Triangle Waveform Linearity. The percentage deviationfrom the best fit straight line on the rising and falling trianglewaveform.

Total Harmonic Distortion. The total harmonic distortion atthe sine wave output.

Typical Performance Curves

FIGURE 11. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 12. FREQUENCY vs SUPPLY VOLTAGE

FIGURE 13. FREQUENCY vs TEMPERATURE FIGURE 14. SQUARE WAVE OUTPUT RISE/FALL TIME vsLOAD RESISTANCE

SUPPLY VOLTAGE (V)

SU

PP

LYC

UR

RE

NT

(mA

)

5 10 15 20 25 305

10

15

20

25oC

125oC

-55oC

SUPPLY VOLTAGE (V)

NO

RM

AL

IZE

DF

RE

QU

EN

CY

5 10 15 20 25 30

0.98

0.99

1.01

1.03

1.00

1.02

TEMPERATURE (oC)

NO

RM

AL

IZE

DF

RE

QU

EN

CY

-50 -25 0 25 75 125

0.98

0.99

1.01

1.03

1.00

1.02

30V

20V10V

20V

30V

10V

LOAD RESISTANCE (kΩ)

106420 80

50

100

150

200

TIM

E(n

s)

125oC

FALL TIME

RISE TIME

25oC

-55oC125oC

25oC

-55oC

9

ICL8038

FIGURE 15. SQUARE WAVE SATURATION VOLTAGE vsLOAD CURRENT

FIGURE 16. TRIANGLE WAVE OUTPUT VOLTAGE vs LOADCURRENT

FIGURE 17. TRIANGLE WAVE OUTPUT VOLTAGE vsFREQUENCY

FIGURE 18. TRIANGLE WAVE LINEARITY vs FREQUENCY

FIGURE 19. SINE WAVE OUTPUT VOLTAGE vs FREQUENCY FIGURE 20. SINE WAVE DISTORTION vs FREQUENCY

Typical Performance Curves (Continued)

LOAD CURRENT (mA)

SA

TU

RA

TIO

NV

OLT

AG

E

106420 8

2

1.5

1.0

0.5

0

125oC

25oC

-55oC

LOAD CURRENT (mA)

NO

RM

AL

IZE

DP

EA

KO

UT

PU

TV

OLT

AG

E

166420 10 201814128

0.8

0.9

1.0

LOAD CURRENT

LOAD CURRENT TO V+

25oC

125oC

-55oC

TO V-

FREQUENCY (Hz)

10K1K10010 1M100K0.6

0.7

0.8

0.9

1.0

1.1

1.2

NO

RM

AL

IZE

DO

UTP

UT

VO

LTA

GE

FREQUENCY (Hz)

10K1K10010 1M100K0.01

0.1

1.0

10.0

LIN

EA

RIT

Y(%

)

FREQUENCY (Hz)

10K1K10010 1M100K

0.9

1.0

1.1

NO

RM

AL

IZE

DO

UTP

UT

VO

LTA

GE

ADJUSTED

FREQUENCY (Hz)

10K1K10010 1M100K

2

4

6

DIS

TO

RT

ION

(%)

0

8

10

12

UNADJUSTED

10

11

ICL8038

Dual-In-Line Plastic Packages (PDIP)

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between Englishand Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 ofPublication No. 95.

4. Dimensions A, A1 and L are measured with the package seated inJEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpen-dicular to datum .

7. eB and eC are measured at the lead tips with the leads uncon-strained. eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambarprotrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -1.14mm).

eA-C-

CL

E

eA

C

eB

eC

-B-

E1INDEX 1 2 3 N/2

N

AREA

SEATING

BASEPLANE

PLANE

-C-

D1

B1B

e

D

D1

AA2

L

A1

-A-

0.010 (0.25) C AM B S

E14.3 (JEDEC MS-001-AA ISSUE D)14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.210 - 5.33 4

A1 0.015 - 0.39 - 4

A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.045 0.070 1.15 1.77 8

C 0.008 0.014 0.204 0.355 -

D 0.735 0.775 18.66 19.68 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6

E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

eA 0.300 BSC 7.62 BSC 6

eB - 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N 14 14 9

Rev. 0 12/93

12

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. Nolicense is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Office HeadquartersNORTH AMERICAIntersil Corporation2401 Palm Bay Rd., Mail Stop 53-204Palm Bay, FL 32905TEL: (321) 724-7000FAX: (321) 724-7240

EUROPEIntersil SAMercure Center100, Rue de la Fusee1130 Brussels, BelgiumTEL: (32) 2.724.2111FAX: (32) 2.724.22.05

ASIAIntersil Ltd.8F-2, 96, Sec. 1, Chien-kuo North,Taipei, Taiwan 104Republic of ChinaTEL: 886-2-2515-8508FAX: 886-2-2515-8369

ICL8038

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-ed adjacent to pin one and shall be located within the shadedarea shown. The manufacturer’s identification shall not be usedas a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall bemeasured at the centroid of the finished lead surfaces, whensolder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. DimensionM applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with apartial lead paddle. For this configuration dimension b3 replacesdimension b2.

5. This dimension allows for off-center lid, meniscus, and glassoverrun.

6. Dimension Q shall be measured from the seating plane to thebase plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

bbb C A - BS

c

Q

L

ASEATING

BASE

D

PLANE

PLANE

-D--A-

-C-

-B-

α

D

E

S1

b2b

A

e

M

c1

b1

(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

eA/2

A

M

S S

ccc C A - BM DS S aaa C A - BM DS S

eA

F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.200 - 5.08 -

b 0.014 0.026 0.36 0.66 2

b1 0.014 0.023 0.36 0.58 3

b2 0.045 0.065 1.14 1.65 -

b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2

c1 0.008 0.015 0.20 0.38 3

D - 0.785 - 19.94 5

E 0.220 0.310 5.59 7.87 5

e 0.100 BSC 2.54 BSC -

eA 0.300 BSC 7.62 BSC -

eA/2 0.150 BSC 3.81 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 6

S1 0.005 - 0.13 - 7

α 90o 105o 90o 105o -

aaa - 0.015 - 0.38 -

bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2, 3

N 14 14 8

Rev. 0 4/94

1/8Sep 2000

IRFP250N-CHANNEL 200V - 0.073Ω - 33A TO-247

PowerMesh II MOSFET

TYPICAL RDS(on) = 0.073Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED NEW HIGH VOLTAGE BENCHMARK GATE CHARGE MINIMIZED

DESCRIPTIONThe PowerMESH II is the evolution of the firstgeneration of MESH OVERLAY . The layout re-finements introduced greatly improve the Ron*areafigure of merit while keeping the device at the lead-ing edge for what concerns swithing speed, gatecharge and ruggedness.

APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING UNINTERRUPTIBLE POWER SUPPLIES (UPS) DC-AC CONVERTERS FOR TELECOM,

INDUSTRIAL, AND LIGHTING EQUIPMENT

ABSOLUTE MAXIMUM RATINGS

(•)Pulse width limited by safe operating area

TYPE VDSS RDS(on) ID

IRFP250 200V < 0.085Ω 33 A

Symbol Parameter Value Unit

VDS Drain-source Voltage (VGS = 0) 200 V

VDGR Drain-gate Voltage (RGS = 20 kΩ) 200 V

VGS Gate- source Voltage ±20 V

ID Drain Current (continuos) at TC = 25°C 33 A

ID Drain Current (continuos) at TC = 100°C 20 A

IDM ( ) Drain Current (pulsed) 132 A

PTOT Total Dissipation at TC = 25°C 180 W

Derating Factor 1.44 W/°C

dv/dt(1) Peak Diode Recovery voltage slope 5 V/ns

Tstg Storage Temperature –65 to 150 °C

Tj Max. Operating Junction Temperature 150 °C

(1)ISD ≤33A, di/dt ≤300A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX.

TO-2471

23

INTERNAL SCHEMATIC DIAGRAM

IRFP250

2/8

THERMAL DATA

AVALANCHE CHARACTERISTICS

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)OFF

ON (1)

DYNAMIC

Rthj-case Thermal Resistance Junction-case Max 0.66 °C/W

Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W

Rthc-sink Thermal Resistance Case-sink Typ 0.1 °C/W

Tl Maximum Lead Temperature For Soldering Purpose 300 °C

Symbol Parameter Max Value Unit

IARAvalanche Current, Repetitive or Not-Repetitive(pulse width limited by Tj max) 33 A

EASSingle Pulse Avalanche Energy(starting Tj = 25 °C, ID = IAR, VDD = 50 V) 600 mJ

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V(BR)DSS Drain-sourceBreakdown Voltage

ID = 250 µA, VGS = 0 200 V

IDSS Zero Gate VoltageDrain Current (VGS = 0)

VDS = Max Rating 1 µA

VDS = Max Rating, TC = 125 °C 50 µA

IGSS Gate-body LeakageCurrent (VDS = 0)

VGS = ±30V ±100 nA


VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 2 3 4 V

RDS(on) Static Drain-source OnResistance

VGS = 10V, ID = 16A 0.073 0.085 Ω

ID(on) On State Drain Current VDS > ID(on) x RDS(on)max,VGS = 10V

33 A


gfs Forward Transconductance VDS > ID(on) x RDS(on)max,ID = 16A

10 25 S

Ciss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 2850 pF

Coss Output Capacitance 420 pF

CrssReverse TransferCapacitance

120 pF

3/8

IRFP250

Safe Operating Area Thermal Impedance

ELECTRICAL CHARACTERISTICS (CONTINUED)

SWITCHING ON

SWITCHING OFF

SOURCE DRAIN DIODE

Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.2. Pulse width limited by safe operating area.


td(on) Turn-on Delay Time VDD = 100V, ID =16 ARG = 4.7Ω, VGS = 10V(see test circuit, Figure 3)

25 ns

tr Rise Time 50 ns

Qg Total Gate Charge VDD = 160V, ID = 33 A,VGS = 10V, RG = 4.7Ω

117 158 nC

Qgs Gate-Source Charge 15 nC

Qgd Gate-Drain Charge 50 nC


tr(Voff) Off-voltage Rise Time VDD = 160V, ID = 16 A,RG = 4.7Ω, VGS = 10V(see test circuit, Figure 5)

60 ns

tf Fall Time 40 ns

tc Cross-over Time 100 ns


ISD Source-drain Current 33 A

ISDM (2) Source-drain Current (pulsed) 132 A

VSD (1) Forward On Voltage ISD = 33 A, VGS = 0 1.6 V

trr Reverse Recovery Time ISD = 33 A, di/dt = 100A/µs,VDD = 100V, Tj = 150°C(see test circuit, Figure 5)

370 ns

Qrr Reverse Recovery Charge 5.4 µC

IRRM Reverse Recovery Current 29 A

IRFP250

4/8

Capacitance Variations

Output Characteristics

Tranconductance

Gate Charge vs Gate-source Voltage

Tranfer Characteristics

Static Drain-Source On Resistance

5/8

IRFP250

Normalized On Resistance vs TemperatureNormalized Gate Thereshold Voltage vs Temp.

Source-drain Diode Forward Characteristics

IRFP250

6/8

Fig. 5: Test Circuit For Inductive Load SwitchingAnd Diode Recovery Times

Fig. 4: Gate Charge test Circuit

Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit

Fig. 3: Switching Times Test Circuit ForResistive Load

7/8

IRFP250

DIM.mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 4.7 5.3 0.185 0.209

D 2.2 2.6 0.087 0.102

E 0.4 0.8 0.016 0.031

F 1 1.4 0.039 0.055

F3 2 2.4 0.079 0.094

F4 3 3.4 0.118 0.134

G 10.9 0.429

H 15.3 15.9 0.602 0.626

L 19.7 20.3 0.776 0.779

L3 14.2 14.8 0.559 0.582

L4 34.6 1.362

L5 5.5 0.217

M 2 3 0.079 0.118

P025P

TO-247 MECHANICAL DATA

IRFP250

8/8

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication aresubject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics productsare not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a trademark of STMicroelectronics

2000 STMicroelectronics – Printed in Italy – All Rights ReservedSTMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

Features• Floating channel designed for bootstrap operation

Fully operational to +500VTolerant to negative transient voltagedV/dt immune

• Gate drive supply range from 12 to 18V• Undervoltage lockout• Current detection and limiting loop to limit driven

power transistor current• Error lead indicates fault conditions and programs

shutdown time• Output in phase with input

• 2.5V, 5V and 15V input logic compatible

DescriptionThe IR2125(S) is a high voltage, high speed powerMOSFET and IGBT driver with over-current limitingprotection circuitry. Proprietary HVIC and latch im-mune CMOS technologies enable ruggedized mono-lithic construction. Logic inputs are compatible withstandard CMOS or LSTTL outputs, down to 2.5Vlogic. The output driver features a high pulse currentbuffer stage designed for minimum driver cross-

CURRENT LIMITING SINGLE CHANNEL DRIVERProduct Summary

VOFFSET 500V max.

IO+/- 1A / 2A

VOUT 12 - 18V

VCSth 230 mV

ton/off (typ.) 150 & 150 ns

Packages

Typical Connection

conduction. The protection circuitry detects over-current in the driven power transistor and limits the gate drive volt-age. Cycle by cycle shutdown is programmed by an external capacitor which directly controls the time intervalbetween detection of the over-current limiting conditions and latched shutdown. The floating channel can be used todrive an N-channel power MOSFET or IGBT in the high or low side configuration which operates up to 500 volts.

VCC VB

CS

HO

VSCOM

IN

ERR

VCC

IN

TOLOAD

up to 500V

IR2125(S)

Data Sheet No. PD60017-O

www.irf.com 1

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electricalconnections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

8-Lead PDIP16-Lead SOIC(Wide Body)

IR2125(S)

2 www.irf.com

Symbol Definition Min. Max. UnitsVB High Side Floating Supply Voltage -0.3 525

VS High Side Floating Offset Voltage VB - 25 VB + 0.3

VHO High Side Floating Output Voltage VS - 0.3 VB + 0.3

VCC Logic Supply Voltage -0.3 25 V

VIN Logic Input Voltage -0.3 VCC + 0.3

VERR Error Signal Voltage -0.3 VCC + 0.3

VCS Current Sense Voltage VS - 0.3 VB + 0.3

dVs/dt Allowable Offset Supply Voltage Transient — 50 V/ns

PD Package Power Dissipation @ TA ≤ +25°C (8 lead PDIP) — 1.0

(16 lead SOIC) — 1.25

RthJA Thermal Resistance, Junction to Ambient (8 lead PDIP) — 125

(16lLead SOIC) — 100

TJ Junction Temperature — 150

TS Storage Temperature -55 150

TL Lead Temperature (Soldering, 10 seconds) — 300

Absolute Maximum RatingsAbsolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measuredunder board mounted and still air conditions.

Symbol Definition Min. Max. UnitsVB High Side Floating Supply Voltage VS + 12 VS + 18

VS High Side Floating Offset Voltage Note 1 500

VHO High Side Floating Output Voltage VS VB

VCC Logic Supply Voltage 0 18

VIN Logic Input Voltage 0 VCC

VERR Error Signal Voltage 0 VCC

VCS Current Sense Signal Voltage VS VB

TA Ambient Temperature -40 125 °C

Note 1: Logic operational for VS of -5 to +500V. Logic state held for VS of -5V to -VBS. (Please refer to the Design TipDT97-3 for more details).

Recommended Operating ConditionsThe Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within therecommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.

W

°C/W

°C

V

www.irf.com 3

IR2125(S)

Symbol Definition Figure Min. Typ. Max. Units Test ConditionsVIH Logic “1” Input Voltage 14 2.2 — —VIL Logic “0” Input Voltage 15 — — 0.8

VCSTH+ CS Input Positive Going Threshold 16 150 230 320VCSTH- CS Input Negative Going Threshold 17 130 200 260

VOH High Level Output Voltage, VBIAS - VO 18 — — 100 IO = 0AVOL Low Level Output Voltage, VO 19 — — 100 IO = 0AILK Offset Supply Leakage Current 20 — — 50 VB = VS = 500V

IQBS Quiescent VBS Supply Current 21 — 400 1000 VIN = VCS = 0V or 5VIQCC Quiescent VCC Supply Current 22 — 700 1200 VIN = VCS = 0V or 5VIIN+ Logic “1” Input Bias Current 23 — 4.5 10 µA VIN = 5VIIN- Logic “0” Input Bias Current 24 — — 1.0 VIN = 0VICS+ “High” CS Bias Current 25 — 4.5 10 VCS = 3VICS- “Low” CS Bias Current 26 — — 1.0 VCS = 0V

VBSUV+ VBS Supply Undervoltage Positive Going 27 8.5 9.2 10.0Threshold

VBSUV- VBS Supply Undervoltage Negative Going 28 7.7 8.3 9.0Threshold

VCCUV+ VCC Supply Undervoltage Positive Going 29 8.3 8.9 9.6Threshold

VCCUV- VCC Supply Undervoltage Negative Going 30 7.3 8.0 8.7Threshold

IERR ERR Timing Charge Current 31 65 100 130 VIN = 5V, VCS = 3VERR < VERR+

IERR+ ERR Pull-Up Current 32 8.0 15 — VIN = 5V, VCS = 3VERR > VERR+

IERR- ERR Pull-Down Current 33 16 30 — VIN = 0VIO+ Output High Short Circuit Pulsed Current 34 1.0 1.6 — VO = 0V, VIN = 5V

PW ≤ 10 µs

IO- Output Low Short Circuit Pulsed Current 35 2.0 3.3 — VO = 15V, VIN = 0VPW ≤ 10 µs

V

mV

mA

V

µA

A

Static Electrical CharacteristicsVBIAS (VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced toCOM. The VO and IO parameters are referenced to VS.

Dynamic Electrical CharacteristicsVBIAS (VCC, VBS) = 15V, CL = 3300 pF and TA = 25°C unless otherwise specified. The dynamic electrical characteristicsare measured using the test circuit shown in Figures 3 through 6.

Symbol Definition Figure Min. Typ. Max. Units Test Conditionston Turn-On Propagation Delay 7 — 150 200 VIN = 0 & 5V

VS = 0 to 600Vtoff Turn-Off Propagation Delay 8 — 150 190tsd ERR Shutdown Propagation Delay 9 — 1.7 2.2 µstr Turn-On Rise Time 10 — 43 60tf Turn-Off Fall Time 11 — 26 35

tcs CS Shutdown Propagation Delay 12 — 0.7 1.2terr CS to ERR Pull-Up Propagation Delay 13 — 9.0 12 CERR = 270 pF

ns

µs

ns

IR2125(S)

4 www.irf.com

Lead DefinitionsSymbol DescriptionVCC Logic and gate drive supplyIN Logic input for gate driver output (HO), in phase with HOERR Serves multiple functions; status reporting, linear mode timing and cycle by cycle logic

shutdownCOM Logic groundVB High side floating supplyHO High side gate drive outputVS High side floating supply return

CS Current sense input to current sense comparator

Functional Block Diagram

Lead Assignments

8 Lead PDIPIR2125

16 Lead SOIC (Wide Body)IR2125S

DOWNSHIFTERS

Q R

UVDETECT

ERRORTIMING

PULSEGEN

UVDETECT

PULSEFILTER

PREDRIVER

PULSEGEN

500 nsBLANK

COMPARATOR

BUFFER

0.23V

HVLEVEL

VB

HO

VS

CS

RS

R Q

VCC

IN

UPSHIFTERS

COM

ERR

LATCHEDSHUTDOWN

1.8V

1.8V

AMPLIFER

-

+

PULSEFILTER

VB

S

SHIFT

HVLEVELSHIFT

Part Number

V CC

IN

ERR

COM

V B

HO

CS

V S

1

2

3

4

8

7

6

5

1

2

7

6

5

4

3

8

16

15

14

13

12

11

10

9

Vcc

IN

ERR

COM VS

CS

HO

VB

www.irf.com 5

IR2125(S)

tsd

HV=10 to 600V

ERR

HO

IR2125(S)

6 www.irf.com

0.00

1.00

2.00

3.00

4.00

5.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

ERR

to Ou

tput S

hutdo

wn D

elay T

ime (

µs)

Max.

Typ.

0

100

200

300

400

500

-50 -25 0 25 50 75 100 125

Temperature (°C)

Turn

-Off D

elay T

ime (

ns)

Max.

Typ.

0

100

200

300

400

500

-50 -25 0 25 50 75 100 125

Temperature (°C)

Turn

-On D

elay T

ime (

ns)

Max.

Typ.

Figure 8A. Turn-Off Time vs. Temperature Figure 8B. Turn-Off Time vs. Voltage

Figure 7A. Turn-On Time vs. Temperature Figure 7B. Turn-On Time vs. Voltage

Figure 9B. ERR to Output Shutdown vs. VoltageFigure 9A. ERR to Output Shutdown vs. Temperature

0

100

200

300

400

500

10 12 14 16 18 20

VBIAS Supply Voltage (V)

Turn

-On T

ime (

ns)

Max.

Typ.

0

100

200

300

400

500

10 12 14 16 18 20


Turn

-Off T

ime (

ns)

Max.

Typ.

0.00

1.00

2.00

3.00

4.00

5.00

10 12 14 16 18 20


ERR

to Ou

tput S

hutdo

wn D

elay T

ime (

µs)

Max.

Typ.

www.irf.com 7

IR2125(S)

0.00

0.40

0.80

1.20

1.60

2.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

CS to

Outp

ut Sh

utdow

n Dela

y Tim

e (µs

)

Max.

Typ.

0

20

40

60

80

100

-50 -25 0 25 50 75 100 125

Temperature (°C)

Turn

-On R

ise T

ime (

ns)

Max.

Typ.

Figure 11A. Turn-Off Fall Time vs. Temperature Figure 11B. Turn-Off Fall Time vs. Voltage

Figure 10A. Turn-On Rise Time vs. Temperature Figure 10B. Turn-On Rise Time vs. Voltage

Figure 12A. CS to Output Shutdown vs. Temperature Figure 12B. CS to Output Shutdown vs. Voltage

0

20

40

60

80

100

10 12 14 16 18 20


Turn

-On R

ise T

ime (

ns)

Max.

Typ.

0

20

40

60

80

100

-50 -25 0 25 50 75 100 125

Temperature (°C)

Turn

-Off F

all T

ime (

ns)

Max.

Typ.

0

20

40

60

80

100

10 12 14 16 18 20


Turn

-Off F

all T

ime (

ns)

Max.

Typ.

0.00

0.40

0.80

1.20

1.60

2.00

10 12 14 16 18 20


CS to

Outp

ut Sh

utdow

n Dela

y Tim

e (µs

)

Max.

Typ.

IR2125(S)

8 www.irf.com

0.00

1.00

2.00

3.00

4.00

5.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

Logic

"1" I

nput

Thre

shold

(V)

Min.

Figure 14A. Logic “1” Input Threshold vs.Temperature

Figure 14B. Logic “1” Input Threshold vs. Voltage

Figure 13B. CS to ERR Pull-Up vs. VoltageFigure 13A. CS to ERR Pull-Up vs. Temperature

Figure 15A. Logic “0” Input Threshold vs.Temperature

Figure 15B. Logic “0” Input Threshold vs. Voltage

0.0

4.0

8.0

12.0

16.0

20.0

10 12 14 16 18 20


CS to

ERR

Pull

-Up D

elay T

ime (

µs)

M ax.

Typ.

0.0

4.0

8.0

12.0

16.0

20.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

CS to

ERR

Pull

-Up D

elay T

ime (

µs)

Max.

Typ.

0.00

1.00

2.00

3.00

4.00

5.00

10 12 14 16 18 20

VCC Logic Supply Voltage (V)

Logic

"1" I

nput

Thre

shold

(V)

Min.

0.00

1.00

2.00

3.00

4.00

5.00

10 12 14 16 18 20


Logic

"0" I

nput

Thre

shold

(V)

Max.

0.00

1.00

2.00

3.00

4.00

5.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

Logic

"0" I

nput

Thre

shold

(V)

Max.

www.irf.com 9

IR2125(S)

0.00

0.20

0.40

0.60

0.80

1.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

High

Leve

l Outp

ut Vo

ltage

(V)

Max.

0

100

200

300

400

500

-50 -25 0 25 50 75 100 125

Temperature (°C)

CS In

put P

ositiv

e Goin

g Thr

esho

ld (m

V)

Min.

Typ.

Max.

Figure 17A. CS Input Threshold (-) vs. Temperature Figure 17B. CS Input Threshold (-) vs. Voltage

Figure 16A. CS Input Threshold (+) vs.Temperature

Figure 16B. CS Input Threshold (+) vs. Voltage

Figure 18A. High Level Output vs. Temperature Figure 18B. High Level Output vs. Voltage

0

100

200

300

400

500

10 12 14 16 18 20

VBS Floating Supply Voltage (V)

CS In

put P

ositiv

e Goin

g Thr

esho

ld (m

V)

Min.

Typ.

Max.

0

100

200

300

400

500

-50 -25 0 25 50 75 100 125

Temperature (°C)

CS In

put N

egati

ve G

oing T

hres

hold

(mV)

Max.

Typ.

Min.

0

100

200

300

400

500

10 12 14 16 18 20


CS In

put N

egati

ve G

oing T

hres

hold

(mV)

Min.

Typ.

Max.

0.00

0.20

0.40

0.60

0.80

1.00

10 12 14 16 18 20


High

Leve

l Outp

ut Vo

ltage

(V)

Max.

IR2125(S)

10 www.irf.com

0.00

0.40

0.80

1.20

1.60

2.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

V BS S

upply

Cur

rent

(mA)

Max.

Typ.

0

100

200

300

400

500

-50 -25 0 25 50 75 100 125

Temperature (°C)

Offse

t Sup

ply Le

akag

e Cur

rent

(µA)

Max.

0.00

0.20

0.40

0.60

0.80

1.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

Low

Leve

l Outp

ut Vo

ltage

(V)

Max.

Figure 20A. Offset Supply Current vs. Temperature Figure 20B. Offset Supply Current vs. Voltage

Figure 19A. Low Level Output vs. Temperature Figure 19B. Low Level Output vs. Voltage

Figure 21A. VBS Supply Current vs. Temperature Figure 21B. VBS Supply Current vs. Voltage

0.00

0.20

0.40

0.60

0.80

1.00

10 12 14 16 18 20


Low

Leve

l Outp

ut Vo

ltage

(V)

Max.

0

100

200

300

400

500

0 100 200 300 400 500

VB Boost Voltage (V)

Offse

t Sup

ply Le

akag

e Cur

rent

(µA)

Max.

0.00

0.40

0.80

1.20

1.60

2.00

10 12 14 16 18 20


V BS S

upply

Cur

rent

(mA)

Max.

Typ.

www.irf.com 11

IR2125(S)

0.00

1.00

2.00

3.00

4.00

5.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

Logic

"0" I

nput

Bias

Cur

rent

(µA)

Max.

0

5

10

15

20

25

-50 -25 0 25 50 75 100 125

Temperature (°C)

Logic

"1" I

nput

Bias

Cur

rent

(µA)

Max.

Typ.

0.00

0.40

0.80

1.20

1.60

2.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

V CC S

upply

Cur

rent

(mA)

Max.

Typ.

Figure 23A. Logic “1” Input Current vs.Temperature

Figure 23B. Logic “1” Input Current vs. Voltage

Figure 22A. VCC Supply Current vs. Temperature Figure 22B. VCC Supply Current vs. Voltage

Figure 24A. Logic “0” Input Current vs.Temperature

Figure 24B. Logic “0” Input Current vs. Voltage

0.00

0.40

0.80

1.20

1.60

2.00

10 12 14 16 18 20


V CC S

upply

Cur

rent

(mA)

Max.

Typ.

0

5

10

15

20

25

10 12 14 16 18 20


Logic

"1" I

nput

Bias

Cur

rent

(µA)

Max.

Typ.

0.00

1.00

2.00

3.00

4.00

5.00

10 12 14 16 18 20


Logic

"0" I

nput

Bias

Cur

rent

(µA)

Max.

IR2125(S)

12 www.irf.com

6.0

7.0

8.0

9.0

10.0

11.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

V BS U

nder

volta

ge Lo

ckou

t + (V

)

Max.

Typ.

Min.

0.00

1.00

2.00

3.00

4.00

5.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

"Low

" CS

Bias

Cur

rent

(µA)

Max.

0.0

5.0

10.0

15.0

20.0

25.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

"High

" CS

Bias

Cur

rent

(µA)

Max.

Typ.

Figure 26A. “Low” CS Bias Current vs. Temperature Figure 26B. “Low” CS Bias Current vs. Voltage

Figure 25A. “High” CS Bias Current vs.Temperature

Figure 25B. “High” CS Bias Current vs. Voltage

Figure 27. VBS Undervoltage (+) vs. Temperature Figure 28. VBS Undervoltage (-) vs. Temperature

0.0

5.0

10.0

15.0

20.0

25.0

10 12 14 16 18 20


"High

" CS

Bias

Cur

rent

(µA)

Max.

Typ.

0.00

1.00

2.00

3.00

4.00

5.00

10 12 14 16 18 20


"Low

" CS

Bias

Cur

rent

(µA)

Max.

6.0

7.0

8.0

9.0

10.0

11.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

VBS

Unde

rvolta

ge Lo

ckou

t - (V

)

Max.

Typ.

Min.

www.irf.com 13

IR2125(S)

0

50

100

150

200

250

-50 -25 0 25 50 75 100 125

Temperature (°C)

ERR

Timing

Cha

rge C

urre

nt (µ

A)

Max.

Typ.

Min.

6.0

7.0

8.0

9.0

10.0

11.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

V CC U

nder

volta

ge Lo

ckou

t + (V

)

Max.

Typ.

Min.

Figure 31A. ERR Timing Charge Current vs.Temperature

Figure 31B. ERR Timing Charge Current vs.Voltage

Figure 29. VCC Undervoltage (+) vs. Temperature Figure 30. VCC Undervoltage (-) vs. Temperature

Figure 32A. ERR Pull-Up Current vs. Temperature Figure 32B. ERR Pull-Up Current vs. Voltage

6.0

7.0

8.0

9.0

10.0

11.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

V CC U

nder

volta

ge Lo

ckou

t - (V

)

Max.

Typ.

Min.

0

50

100

150

200

250

10 12 14 16 18 20


ERR

Timing

Cha

rge C

urre

nt (µ

A)

Min.

Typ.

Max.

0.0

5.0

10.0

15.0

20.0

25.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

ERR

Pull-U

p Cu

rrent

(mA) Typ.

Min.

0.0

5.0

10.0

15.0

20.0

25.0

10 12 14 16 18 20


ERR

Pull-U

p Cu

rrent

(mA)

Min.

Typ.

IR2125(S)

14 www.irf.com

0.00

1.00

2.00

3.00

4.00

5.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

Outpu

t Sink

Cur

rent

(A)

Typ.

Min.

0.00

0.50

1.00

1.50

2.00

2.50

-50 -25 0 25 50 75 100 125

Temperature (°C)

Outpu

t Sou

rce C

urre

nt (A

)

Typ.

Min.

0

10

20

30

40

50

-50 -25 0 25 50 75 100 125

Temperature (°C)

ERR

Pull-D

own C

urre

nt (m

A) Typ.

Min.

Figure 34A. Output Source Current vs.Temperature

Figure 34B. Output Source Current vs. Voltage

Figure 33A. ERR Pull-Down Current vs.Temperature Figure 33B. ERR Pull-Down Current vs. Voltage

Figure 35A. Output Sink Current vs.Temperature Figure 35B. Output Sink Current vs. Voltage

0

10

20

30

40

50

10 12 14 16 18 20


ERR

Pull-D

own C

urre

nt (m

A)

Max.

Typ.

0.00

0.50

1.00

1.50

2.00

2.50

10 12 14 16 18 20


Outpu

t Sou

rce C

urre

nt (A

)

Min.

Typ.

0.00

1.00

2.00

3.00

4.00

5.00

10 12 14 16 18 20


Outpu

t Sink

Cur

rent

(A)

Min.

Typ.

www.irf.com 15

IR2125(S)

Figure 37. Maximum VS Negative Offset vs. SupplyVoltage

-15.00

-12.00

-9.00

-6.00

-3.00

0.00

10 12 14 16 18 20


V S O

ffset

Supp

ly Vo

ltage

(V)

Typ.

Figure 36A. Turn-On Time vs. Input Voltage Figure 36B. Turn-Off Time vs. Input Voltage

0

50

100

150

200

250

300

0 2 4 6 8 10 12 14 16 18 20

Input Voltage (V)

Tu

rn-O

n D

ela

y T

ime

(n

s)

0

50

100

150

200

250

300

0 2 4 6 8 10 12 14 16 18 20

Max.

Typ.

Input Voltage (V)

Tu

rn-O

ff D

ela

y T

ime

(n

s)

IR2125(S)

16 www.irf.com

WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 5/23/2002

01-601401-3003 01 (MS-001AB)8-Lead PDIP

Case outlines

16-Lead SOIC (wide body) 01 601501-3014 03 (MS-013AA)

“tapped” - rovira i virgili universitydeeea.urv.cat/public/propostes/pub/pdf/218pub.pdf ·...

Documents