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INTRODUCTION TOCMOS VLSI

DESIGN

SRAM

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CMOS VLSI Design

OUTLINE Memory Arrays

 SRAM Architecture SRAM Cell Decoders

Column Circuitry

Multile !orts

 Serial Access Memories

SRAM Slide "

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CMOS VLSI Design

MEMOR# ARRA#S

SRAM Slide $

Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory

(CAM)

Read/Write Memory

(RAM)(Volatile)

Read Only Memory

(ROM)(Nonvolatile)

Static RAM

(SRAM)

Dynamic RAM

(DRAM)

Shift Reisters !"e"es

#irst $n

#irst O"t

(#$#O)

%ast $n

#irst O"t

(%$#O)

Serial $n

&arallel O"t

(S$&O)

&arallel $n

Serial O"t

(&$SO)

Mas' ROM &rorammable

ROM

(&ROM)

rasable

&rorammable

ROM

(&ROM)

lectrically

rasable

&rorammable

ROM

(&ROM)

#lash ROM

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CMOS VLSI Design

ARRA# ARC%ITECTURE "n words o& "m bits each

 I& n '' m( &old )y "* into &e+er rows o& more columns

 Good re,ularity - easy to desi,n

 Very hi,h density i& ,ood cells are used

SRAM Slide .

r  o)  d  e c  o d  er 

col"mn

decoder 

n

n*''

+m bits

col"mn

circ"itry

bitline conditionin

memory cells,

+n*' ros -

+m.' col"mns

bitlines

ordlines

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CMOS VLSI Design

/"T SRAM CELL 0asic )uildin, )loc*1 SRAM Cell %olds one )it o& in&ormation( li*e a latch

Must )e read and +ritten

 /"2transistor 3/"T4 SRAM cell Use a simle latch connected to )itline

.5 6 78 λ unit cell

SRAM Slide 8

bit

rite

riteb

read

readb

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CMOS VLSI Design

5T SRAM CELL Cell si9e accounts &or most o& array si9e Reduce cell si9e at e6ense o& comle6ity

 5T SRAM Cell Used in most commercial chis

Data stored in cross2couled in:erters

 Read1 !rechar,e )it( )it;)

Raise +ordline

 

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CMOS VLSI Design

SRAM READ !rechar,e )oth )itlines hi,h

  Then turn on +ordline

 One o& the t+o )itlines +ill )e ulled do+n )y the cell

 E61 A = >( A;) = / )it dischar,es( )it;) stays hi,h

0ut A )ums u sli,htly

 Read stability  A must not ?i

SRAM Slide 7

bit   bitb

N0

N+&0

 A

&+

N1

N2

 Ab

ord

343

345

043

045

3   033 +33 133 233 533 633

time (7s)

ord   bit

 A

 Ab bitb

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CMOS VLSI Design

SRAM READ !rechar,e )oth )itlines hi,h

  Then turn on +ordline

 One o& the t+o )itlines +ill )e ulled do+n )y the cell

 E61 A = >( A;) = / )it dischar,es( )it;) stays hi,h

0ut A )ums u sli,htly

 Read stability  A must not ?i

N/ '' N"

SRAM Slide @

bit   bitb

N0

N+&0

 A

&+

N1

N2

 Ab

ord

343

345

043

045

3   033 +33 133 233 533 633

time (7s)

ord   bit

 A

 Ab bitb

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CMOS VLSI Design

SRAM ( A;) = /( )it = /( )it;) = > orce A;) lo+( then A rises hi,h

 Writability  Must o:ero+er &eed)ac* in:erter

SRAM Slide B

time (7s)

ord

 A

 Ab

bitb

343

345

043

045

3   033 +33 133 233 533 633 833

bit   bitb

N0

N+&0

 A

&+

N1

N2

 Ab

ord

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CMOS VLSI Design

SRAM ( A;) = /( )it = /( )it;) = > orce A;) lo+( then A rises hi,h

 Writability  Must o:ero+er &eed)ac* in:erter

N" '' !/

SRAM Slide />

time (7s)

ord

 A

 Ab

bitb

343

345

043

045

3   033 +33 133 233 533 633 833

bit   bitb

N0

N+&0

 A

&+

N1

N2

 Ab

ord

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CMOS VLSI Design

SRAM SIING %i,h )itlines must not o:ero+er in:erters durin,reads

 0ut lo+ )itlines must +rite ne+ :alue into cell

SRAM Slide //

bit   bitb

 med

 A

ea'

stron

med

 Ab

ord

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CMOS VLSI Design

SRAM COLUMN EAM!LERead

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CMOS VLSI Design

SRAM LA#OUT Cell si9e is critical1 "5 6 .8 λ 3e:en smaller in industry4  Tile cells sharin, VDD( GND( )itline contacts

SRAM Slide /$

VDD

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CMOS VLSI Design

DECODERS n1"n decoder consists o& "n n2inut AND ,ates One needed &or each ro+ o& memory

0uild AND &rom NAND or NOR ,ates

Static CMOS !seudo2nMOS

SRAM Slide /.

ord3

ord0

ord+

ord1

 A3 A0

 A0

ord

 A30 0

0/+

+

2

>

06ord

 A3

 A0

0

0

00

2

>ord3

ord0

ord+

ord1

 A3 A0

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CMOS VLSI Design

DECODER LA#OUT Decoders must )e itch2matched to SRAM cell Reuires :ery s*inny ,ates

SRAM Slide /8

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CMOS VLSI Design

LARGE DECODERS or n ' .( NAND ,ates )ecome slo+ 0rea* lar,e ,ates into multile smaller ,ates

SRAM Slide /5

ord3

ord0

ord+

ord1

ord05

 A3 A0 A+ A1

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CMOS VLSI Design

!REDECODING Many o& these ,ates are redundant actor out common

,ates into redecoder

Sa:es area

Same ath eFort

SRAM Slide /7

 A3

 A0

 A+

 A1

ord0

ord+

ord1

ord05

ord3

0 of 2 hot

7redecoded lines

7redecoders

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CMOS VLSI Design

COLUMN CIRCUITR# Some circuitry is reuired &or each column 0itline conditionin,

Sense amliers

Column multile6in,

SRAM Slide /@

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CMOS VLSI Design

0ITLINE CONDITIONING !rechar,e )itlines hi,h )e&ore reads

 Euali9e )itlines to minimi9e :olta,e diFerence +henusin, sense amliers

SRAM Slide /B

φ

bit bitb

φ

bit bitb

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CMOS VLSI Design

SENSE AM!LIIERS 0itlines ha:e many cells attached E61 $"2*)it SRAM has "85 ro+s 6 /"@ cols

/"@ cells on each )itline

 td ∝ 3CHI4 ∆V E:en +ith shared diFusion contacts( 5.C o& diFusion caacitance

3)i, C4

Dischar,ed slo+ly throu,h small transistors 3small I4

 Sense amplifers are tri,,ered on small :olta,e s+in,3reduce ∆V4

SRAM Slide ">

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CMOS VLSI Design

DIERENTIAL !AIR AM! DiFerential air reuires no cloc*

 0ut al+ays dissiates static o+er

SRAM Slide "/

bit bitb

senseb   sense

N0 N+

N1

&0 &+

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CMOS VLSI Design

CLOCED SENSE AM! Cloc*ed sense am sa:es o+er

 Reuires sense;cl* a&ter enou,h )itline s+in,

 Isolation transistors cut oF lar,e )itline caacitance

SRAM Slide ""

bitbbit

sense senseb

sensecl'   isolation

transistors

reenerative

feedbac'