DEPARTAMENTODEAUTOMÁTICA
ARQUITECTURAYTECNOLOGÍADECOMPUTADORES
GradoenIngenieríaInformática
FUNDAMENTOSDETECNOLIGÍADECOMPUTADORES
CONTADORES ASÍNCRONOS
Binario de 3 bits
!
DEPARTAMENTO*DE*AUTOMÁTICA*
ARQUITECTURA*Y*TECNOLOGÍA*DE*COMPUTADORES*
!
Grado*en*Ingeniería*Informática*
FUNDAMENTOS*DE*TECNOLIGÍA*DE*COMPUTADORES*
Curso*Académico*2012/2013!
!
CONTADORES ASÍNCRONOS
Binario de 3 bits
!!!!!!!!!
Binario de 4 bits
Flip-flops activos en flanco de bajada (atención a las entradas de clock de los flip-flops, ahora es Q y no Q negado)
Binario de 4 bits
Flip-flops activos en flanco de bajada (atención a las entradas de clock de los flip-flops, ahora es Q y no Q negado)
!!!!!!!!!!
Contador de décadas asíncrono
Contador de décadas asíncrono
!!
!!!!!!!!!
Contador módulo 12 asíncrono
SN54/74LS93
5-90FAST AND LS TTL DATA
DECADE COUNTER;DIVIDE-BY-TWELVE COUNTER;4-BIT BINARY COUNTER
The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed4-bit ripple type counters partitioned into two sections. Each counter has a di-vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) ordivide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-tion on the clock inputs. Each section can be used separately or tied together(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All ofthe counters have a 2-input gated Master Reset (Clear), and the LS90 alsohas a 2-input gated Master Set (Preset 9).• Low Power Consumption . . . Typically 45 mW• High Count Rates . . . Typically 42 MHz• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary• Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES LOADING (Note a)
HIGH LOW
CP0 Clock (Active LOW going edge) Input to÷2 Section
0.5 U.L. 1.5 U.L.
CP1 Clock (Active LOW going edge) Input to÷5 Section (LS90), ÷6 Section (LS92)
0.5 U.L. 2.0 U.L.
CP1 Clock (Active LOW going edge) Input to÷8 Section (LS93)
0.5 U.L. 1.0 U.L.
MR1, MR2 Master Reset (Clear) Inputs 0.5 U.L. 0.25 U.L.MS1, MS2 Master Set (Preset-9, LS90) Inputs 0.5 U.L. 0.25 U.L.Q0 Output from ÷2 Section (Notes b & c) 10 U.L. 5 (2.5) U.L.Q1, Q2, Q3 Outputs from ÷5 (LS90), ÷6 (LS92),
÷ 8 (LS93) Sections (Note b)10 U.L. 5 (2.5) U.L.
NOTES:a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)b. Temperature Ranges.c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
SN54/74LS90SN54/74LS92SN54/74LS93
DECADE COUNTER;DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTERLOW POWER SCHOTTKY
J SUFFIXCERAMIC
CASE 632-08
N SUFFIXPLASTIC
CASE 646-06
141
141
ORDERING INFORMATIONSN54LSXXJ CeramicSN74LSXXN PlasticSN74LSXXD SOIC
141
D SUFFIXSOIC
CASE 751A-02
LOGIC SYMBOL
1 22
VCC = PIN 5GND = PIN 10NC = PINS 4, 13
VCC = PIN 5GND = PIN 10NC = PINS 2, 3, 4, 13
VCC = PIN 5GND = PIN 10NC = PIN 4, 6, 7, 13
LS90 LS92 LS936 7
1 2
14
1
1 2
2 3
MSCP0CP1
MR Q0 Q1 Q2 Q3
12 9 8 11 6 7
14
1
1
CP0CP1
MR Q0 Q1 Q2 Q3
12 9 811
14
1
2 3
CP0CP1
MR Q0 Q1 Q2 Q3
12 9 8 11
5-93FAST AND LS TTL DATA
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
LS90MODE SELECTION
RESET/SET INPUTS OUTPUTSMR1 MR2 MS1 MS2 Q0 Q1 Q2 Q3
HHXLXLX
HHXXLXL
LXHLXXL
LLH
LLL
LLL
LLH
CountCountCountCount
XLHXLLX
H = HIGH Voltage LevelL = LOW Voltage LevelX = Don’t Care
LS92 AND LS93MODE SELECTION
RESETINPUTS OUTPUTS
MR1 MR2 Q0 Q1 Q2 Q3HLHL
HHLL
L L L LCountCountCount
H = HIGH Voltage LevelL = LOW Voltage LevelX = Don’t Care
LS90BCD COUNT SEQUENCE
COUNTOUTPUT
Q0 Q1 Q2 Q30123456789
LHLHLHLHLH
LLHHLLHHLL
LLLLHHHHLL
LLLLLLLLHH
NOTE: Output Q0 is connected to InputCP1 for BCD count.
LS92TRUTH TABLE
COUNTOUTPUT
Q0 Q1 Q2 Q30123456789
1011
LHLHLHLHLHLH
LLHHLLLLHHLL
LLLLHHLLLLHH
LLLLLLHHHHHH
NOTE: Output Q0 is connected to InputCP1.
LS93TRUTH TABLE
COUNTOUTPUT
Q0 Q1 Q2 Q30123456789
101112131415
LHLHLHLHLHLHLHLH
LLHHLLHHLLHHLLHH
LLLLHHHHLLLLHHHH
LLLLLLLLHHHHHHHH
NOTE: Output Q0 is connected to InputCP1.
5-91FAST AND LS TTL DATA
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
LOGIC DIAGRAM
MS1MS2
MR1MR2
CP0
CP1
Q0 Q1 Q2 Q3
MR1
CP0
CP1
Q0 Q1 Q2 Q3MR2
LS90
MR1
CP0
CP1
Q0 Q1 Q2 Q3MR2
SDJCPK
Q
QCD
SDRCPS
Q
QCD
SDJCPK
Q
QCD
SDJCPK
Q
QCD
JCPK
Q
QCD
JCPK
Q
QCD
JCPK
Q
QCD
JCPK
Q
QCD
JCPK
Q
QCD
JCPK
Q
QCD
JCPK
Q
QCD
JCPK
Q
QCD
14
1112
1
2
6
7
93
8
14
13
12
11
10
9
1
2
3
4
5
6
87
CP0NC
Q0Q3GND
Q1Q2
CP1MR1MR2
NC
VCCMS1MS2
CONNECTION DIAGRAMDIP (TOP VIEW)
NC = NO INTERNAL CONNECTIONNOTE:The Flatpak version has the samepinouts (Connection Diagram) asthe Dual In-Line Package.
14
1
6
712 11 9 8
LOGIC DIAGRAM
LS9214
13
12
11
10
9
1
2
3
4
5
6
87
CP0NC
Q0Q1GND
Q2Q3
CP1NC
NC
NC
VCCMR1MR2
CONNECTION DIAGRAMDIP (TOP VIEW)
NC = NO INTERNAL CONNECTIONNOTE:The Flatpak version has the samepinouts (Connection Diagram) asthe Dual In-Line Package.
LOGIC DIAGRAMLS93
VCC = PIN 5GND = PIN 10
= PIN NUMBERS
VCC = PIN 5GND = PIN 10
= PIN NUMBERS
VCC = PIN 5GND = PIN 10
= PIN NUMBERS
14
1
2
312 9 8 11
14
13
12
11
10
9
1
2
3
4
5
6
87
CP0NC
Q0Q3GND
Q1Q2
CP1MR1MR2
NC
VCCNC
NC
CONNECTION DIAGRAMDIP (TOP VIEW)
NC = NO INTERNAL CONNECTIONNOTE:The Flatpak version has the samepinouts (Connection Diagram) asthe Dual In-Line Package.
5-93FAST AND LS TTL DATA
SN54/74LS90 • SN54/74LS92 • SN54/74LS93
LS90MODE SELECTION
RESET/SET INPUTS OUTPUTSMR1 MR2 MS1 MS2 Q0 Q1 Q2 Q3
HHXLXLX
HHXXLXL
LXHLXXL
LLH
LLL
LLL
LLH
CountCountCountCount
XLHXLLX
H = HIGH Voltage LevelL = LOW Voltage LevelX = Don’t Care
LS92 AND LS93MODE SELECTION
RESETINPUTS OUTPUTS
MR1 MR2 Q0 Q1 Q2 Q3HLHL
HHLL
L L L LCountCountCount
H = HIGH Voltage LevelL = LOW Voltage LevelX = Don’t Care
LS90BCD COUNT SEQUENCE
COUNTOUTPUT
Q0 Q1 Q2 Q30123456789
LHLHLHLHLH
LLHHLLHHLL
LLLLHHHHLL
LLLLLLLLHH
NOTE: Output Q0 is connected to InputCP1 for BCD count.
LS92TRUTH TABLE
COUNTOUTPUT
Q0 Q1 Q2 Q30123456789
1011
LHLHLHLHLHLH
LLHHLLLLHHLL
LLLLHHLLLLHH
LLLLLLHHHHHH
NOTE: Output Q0 is connected to InputCP1.
LS93TRUTH TABLE
COUNTOUTPUT
Q0 Q1 Q2 Q30123456789
101112131415
LHLHLHLHLHLHLHLH
LLHHLLHHLLHHLLHH
LLLLHHHHLLLLHHHH
LLLLLLLLHHHHHHHH
NOTE: Output Q0 is connected to InputCP1.
CONTADORES SÍNCRONOS
Binario de 4 bits
A B C D E F G H J K
B C D E F G H J KA
FILE NAME:
BY:
DATE:
PAGE:
sincronos2.pdsprj17/11/2014
@AUTHOR
C:\Users\JoséAntonio\Documents\sincronos2.pdsprjPATH: 1 of 1
REV: @REV TIME: 16:16:56
DESIGN TITLE: sincronos2.pdsprj
0
1
2
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
3
9
J9
Q11
CLK6
K12
Q10
S7
R8
J4
Q15
CLK1
K16
Q14
S2
R3
J4
Q15
CLK1
K16
Q14
S2
R3
J9
Q11
CLK6
K12
Q10
S7
R8
relojQ0 Q1 Q2 Q3
J
CLK
Q
Q
K
J
CLK
Q
Q
K
J
CLK
Q
Q
K
J
CLK
Q
Q
K
reloj
reloj
Q0 Q1 Q2 Q3
J
CLK
Q
Q
K
J
CLK
Q
Q
K
J
CLK
Q
Q
K
Q0 Q1 Q2
up/down
reloj
Q0
Q1
Q2
Q3
Contador de décadas síncrono A B C D E F G H J K
B C D E F G H J KA
FILE NAME:
BY:
DATE:
PAGE:
sincronos2.pdsprj17/11/2014
@AUTHOR
C:\Users\JoséAntonio\Documents\sincronos2.pdsprjPATH: 1 of 1
REV: @REV TIME: 16:16:56
DESIGN TITLE: sincronos2.pdsprj
0
1
2
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
3
9
J9
Q11
CLK6
K12
Q10
S7
R8
J4
Q15
CLK1
K16
Q14
S2
R3
J4
Q15
CLK1
K16
Q14
S2
R3
J9
Q11
CLK6
K12
Q10
S7
R8
relojQ0 Q1 Q2 Q3
J
CLK
Q
Q
K
J
CLK
Q
Q
K
J
CLK
Q
Q
K
J
CLK
Q
Q
K
reloj
reloj
Q0 Q1 Q2 Q3
J
CLK
Q
Q
K
J
CLK
Q
Q
K
J
CLK
Q
Q
K
Q0 Q1 Q2
up/down
J0 = K0 =1
J1 = K1 =Q0Q3
J2 = K2 =Q0Q1
J3 = K3 =Q0Q1Q2 +Q0Q3
reloj 1 2 3 4 5 6 7 8 9 0 1
Q0
Q1
Q2
Q3
Contador síncrono ascendente/descendente
A B C D E F G H J K
B C D E F G H J KA
FILE NAME:
BY:
DATE:
PAGE:
sincronos2.pdsprj17/11/2014
@AUTHOR
C:\Users\JoséAntonio\Documents\sincronos2.pdsprjPATH: 1 of 1
REV: @REV TIME: 16:16:56
DESIGN TITLE: sincronos2.pdsprj
0
1
2
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
3
9
J9
Q11
CLK6
K12
Q10
S7
R8
J4
Q15
CLK1
K16
Q14
S2
R3
J4
Q15
CLK1
K16
Q14
S2
R3
J9
Q11
CLK6
K12
Q10
S7
R8
relojQ0 Q1 Q2 Q3
J
CLK
Q
Q
K
J
CLK
Q
Q
K
J
CLK
Q
Q
K
J
CLK
Q
Q
K
reloj
reloj
Q0 Q1 Q2 Q3
J
CLK
Q
Q
K
J
CLK
Q
Q
K
J
CLK
Q
Q
K
Q0 Q1 Q2
up/down
up/down
reloj 1 2 3 4 5 6 5 4 3 2 3 4 5 6
Q0
Q1
Q2