aportaciones mediante implementaciÓn basada en sistemas embebidos al control digital de...

8/15/2019 APORTACIONES MEDIANTE IMPLEMENTACIÓN BASADA EN SISTEMAS EMBEBIDOS AL CONTROL DIGITAL DE CONVERTI…

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d

1 − d


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n

vout

N v N i


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d + δ

d · k2

1 − (1 − d) · k3

d

d1

d

2

1 − δ

11+δ

d1 d2

da db

da db dc

d + δ 1 d · k2 1 − (1 − d) · k3

V g = 230 V 1 − d

P = 147 W

300 W

V g =

230 V P = 300 W

V out = 400 V

V g = 120 V

P = 176 W

V out = 300 V

230 V

120 V


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200 ms

n

vout

d 1 − d

V g 230 V

Da, Db, Dc


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0

50

100

150

200

250

300

350

400

450

0 5 10 15 20 25 30

t(ms)

tensión de salida

tensión de entrada

corriente de entrada

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1

0 5 10 15 20 25 30

t(ms)

ciclo de trabajo


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VHDL Testbench

Digital Circuit

(VHDL)

Sense

Time

control

Clock

Reset

Control

ADC

Model

Analog simulator (PSIM) Digital simulator (Modelsim)

Power Stage(analog circuit)

ModelSim-PSIM co-simulation scheme, including the

comm unicat ion sch eme (DLLb lock in PSIM and FLI block in ModelSim)

Analog simulation

Sense

data

Control

data

Sense

data

Control

data

Digital simulation

1 2

3

3

Analog

simulator

(PSIM)

Digital

simulator

(Modelsim)

N cycles, N= ∆t/clkperiod

1 simulatonstep (∆t)InstanttN InstanttN+1= tN+∆t

Synchronization and com munication diagram

2,18

3, 85

10


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SPICE Model

VHDL-AMS Model

VHDL Model

SPICE Model SPICE Model

Power Converter

& Power source

QL

Load

L R

INDUCTOR

Electrical Sensors

ADCs

VoltageCurrent

Digital Circuit

(Power computation

Gating signals …)

QH

QL

Control

Digital data

I / O

I n t e r f a c e

P o w e r B l o c k

D i g i t a l B l o c k

I n t e r f a c e B l o c k

SPICE ModelSPICE Model

VHDL-AMS ModelVHDL-AMS Model

VHDL ModelVHDL Model

SPICE ModelSPICE Model SPICE ModelSPICE Model

Power Converter

& Power source

QLQL

Load

L R

INDUCTOR

Electrical Sensors

ADCs

VoltageCurrent

Digital Circuit

(Power computation

Gating signals …)

QH

QL

Control

Digital data

I / O

I n t e r f a c e

P o w e r B l o c k

D i g i t a l B l o c k

I n t e r f a c e B l o c k

µs

10 kH z

50 µs


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100 kH z

ns


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100 kH z

100 Hz

vout iin

vg

gin


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GID (s) = V out

Ls

GID (s)

V out L

GV G(s) =

v2gR

2·V outRC 2 s + 1

GV G(s)

vg V out

f sw 100 k Hz

resoluciónP W M 1000

L 5 mH

C 100 µF

P out 300 W

V out 400 V

100 M Hz


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0,5z−0,4844z−1

10 µs 6,33 k Hz 472 µs

3,052·10−5z−1,526·10−5

z−1 10 ms 6,71 H z 109 ms

f CLK 100 M Hz

10 ns

472 µs

109 ms


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vg

iin D

Q C R

+

-

L

vout iin

iL

vL = L · diLdt

k

iL(k) = iL(k − 1) + ∆t

L · vL

iL(k) k ∆t

vL

iC

iC = C · dvout

dt


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k

vout(k) = vout(k − 1) + ∆tC

· iC

∆t

∆tL

∆tC iC

iC iR

iL − iR

iR = vout

R

iR

iL

iL(k) = iL(k − 1) + ∆tL

· vg

vout(k) = vout(k − 1) − ∆tC

· iR

iL(k) = iL(k − 1) + ∆tL

· (vg − vout)

vout(k) = vout(k − 1) + ∆tC

· (iL − iR)

iL(k) = 0

vout(k) = vout(k − 1) − ∆tC

· iR


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iL i

∗

L

i∗L = L

∆t · iL

i∗L(k) = i∗

L(k − 1) + vL

v∗out = C

∆t · vout

v∗out(k) = v∗

out(k − 1) + iC


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iC i

∗

C

iC v∗out v∗∗out

v∗∗out = L

∆tv∗out =

C

∆t

L

∆t · vout

v∗∗out(k) = v∗∗

out(k − 1) + i∗C

i∗C vL

i∗L(k) = i∗

L(k − 1) + vgv∗∗out(k) = v

∗∗

out(k − 1) − i∗R

i∗L(k) = i∗

L(k − 1) + vg − voutv∗∗out(k) = v

∗∗

out(k

− 1) + i∗L

−i∗R

i∗L(k) = 0

v∗∗out(k) = v∗∗

out(k − 1) − i∗R

i∗L vout


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vout v∗∗

out

vout = ∆t

C

∆t

L · v∗∗out

iL

iL


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iLAdd voutAuxAdd dtL dtC ∆tL ∆tC

iLAdd voutAuxAdd


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32

64

vg 1000

vg


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1

1 + 5 + 3

2−Y

vout 2

−Y

vout 256,125 V i∗

R

iR ∆t


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vg 13 ± 511,875 V 0,125 V vout 13 ± 511,875 A 0,125 V i∗R 13

∆tL

± 8,387 A 2,048 · 10−3 Av∗out 34

∆tL

∆tC

± 1759,219 V 2,048 · 10−7 V voutSat

∗ 18

∆tL

∆tC

± 1759,205 V 0,013 V i∗L 26

∆tL

± 8,389 A 2,5 · 10−7 AiLSat

∗ 18

∆tL

± 8,389 A 6,4 · 10−5 A

iR 4,196352 A

iLAdd∗

i∗L

12

12

1

iLAdd

∗

i

∗

L

26

2,5 · 10−7

A

iR

26

i∗L 13

26

13

i∗L 13 2,048 mA

0,25 µA


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26

26

13

26

26

13

i∗R

v

outAdd∗∗

i∗L

v∗∗out

v∗∗out

18

v∗∗out

18

v∗∗out 18

13

i∗L

vout iin

i∗R vg mosfet i∗

R

mosfet

vg


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